TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 140

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

Up
counter
Comparator output
(Match detect)
X: Don’t care, −: No change
<TA01RUN>
TA01RUN
TA01MOD
TA1REG
TA1FFCR
PCCR
PCFC
TA01RUN
Comparator
Bit7 to Bit2
UC1 clear
TA01RUN
TA1OUT
INTTA1
TA1FF
Example: To output a 2.4-μs square wave pulse from the TA1OUT pin at f
timing
2.
Bit1
Bit0
φT1
Generating a 50 % duty ratio square wave pulse
its status output via the timer output pin (TA1OUT).
Figure 3.7.10 Square Wave Output Timing Chart (50 % Duty)
← −
← 0
← 0
← X
← −
← −
← −
The state of the timer flip-flop (TA1FF1) is inverted at constant intervals and
0
7
use the following procedure to make the appropriate register settings. This
example uses TMRA1; however, either TMRA0 or TMRA1 may be used.
6
X
0
0
X
−
−
X
5
X
X
0
X
−
−
X
1
4
X
X
0
X
−
−
X
3
−
0
0
1
−
−
−
2
2
−
1
0
0
−
−
1
92CH21-138
3
1
0
−
1
1
−
−
1
0
−
−
1
1
1
1
−
0
1.2 μs at f
1
Stop TMRA1 and clear it to “0”.
Select 8-bit timer mode and select φT1 (=(16/fc)s at f
MHz) as the input clock.
Set the timer register to 2.4 μs ÷ φT1 ÷ 2 = 3
Clear TA1FF to “0” and set it to invert on the match detect
signal from TMRA1.
Set PC0 to function as the TA1OUT pin.
Start TMRA1 counting.
C
2
= 40 MHz
3
0
1
2
3
TMP92CH21
C
2009-06-19
0
= 40 MHz,
C
= 40