TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 58

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

*INT0 level enable
Interrupt
Symbol
Note 1: Disable INT0 request before changing INT0 pin mode from level sense to edge sense.
Note 2: See electrical characteristics in section 4 for external interrupt input pulse width.
INT0
INT1
INT2
INT3
INT4
INT5
IIMC
0
1
Edge detect INT
“H” level INT
Setting example:
Interrupt
Name
Name Address
control
X: Don’t care, −: No change.
mode
input
PC0
PC1
PC2
PC3
Pin
P96
P97
(2) External interrupt control
DI
LD
LD
NOP
NOP
NOP
EI
(Prohibit
RMW)
F6H
(IIMC), XXXXXX00B ; Switches from level to edge.
(INTCLR), 0AH
INT5EDGE
0: Rising
1: Falling
Mode
I5EDGE
Settings of External Interrupt Pin Function
Rising edge
Falling edge
High level
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
W
7
0
INT4EDGE
0: Rising
1: Falling
I4EDGE
W
6
0
; Clears interrupt request flag.
; Wait EI execution
92CH21-56
<I0LE> = 0, <I0EDGE> = 0
<I0LE> = 0, <I0EDGE> = 1
<I0LE> = 1
<I1EDGE> = 0
<I1EDGE> = 1
<I2EDGE> = 0
<I2EDGE> = 1
<I3EDGE> = 0
<I3EDGE> = 1
<I4EDGE> = 0
<I4EDGE> = 1
<I5EDGE> = 0
<I5EDGE> = 1
INT3EDGE
0: Rising
1: Falling
I3EDGE
W
5
0
INT2EDGE
0: Rising
1: Falling
I2EDGE
W
4
0
INT1EDGE
0: Rising
1: Falling
I1EDGE
Setting Method
W
3
0
INT0EDGE
0: Rising
1: Falling
I0EDGE
W
2
0
0: INT0
1: INT0
edge
mode
level
mode
I0LE
R/W
1
0
TMP92CH21
2009-06-19
Always
write “0”
R/W
0
−
0