TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 143

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

TA0REG-WR
TA01RUN<TA0RDE>
(Value to be compared)
TA01MOD<TA0CLK1:0>
Match with TA0REG
Match with TA1REG
φT1
φT4
φT16
Selector
output each time the 8-bit up counter (UC0) matches the value in one of the timer
registers TA0REG or TA1REG.
TA01RUN<TA1RUN> should be set to “1” so that UC1 is set for counting.
will be shifted into TA0REG each time TA1REG matches UC0.
varied).
and up counter
Register buffer
In this mode a programmable square wave is generated by inverting the timer
The value set in TA0REG must be smaller than the value set in TA1REG.
Although the up counter for TMRA1 (UC1) is not used in this mode,
Figure 3.7.14 shows a block diagram representing this mode.
If the TA0REG double buffer is enabled in this mode, the value of the register buffer
Use of the double buffer facilitates the handling of low duty waves (when duty is
TA0REG
Selector
Shift trigger
Figure 3.7.14 Block Diagram of 8-Bit PPG Output Mode
Register buffer
Comparator
Figure 3.7.15 Operation of Register Buffer
TA0REG
Internal data bus
up counter
(Up counter = Q
(UC0)
8-bit
92CH21-141
Q
Comparator
1
TA1REG
1
)
Q
TA01RUN<TA0RUN>
2
(Up counter = Q
Shift from register buffer
TA1OUT
TA1FF
2
Inversion
)
Q
2
TA0REG (Register buffer)
write
INTTA0
INTTA1
TA1FFCR<TA1FFIE>
Q
3
TMP92CH21
2009-06-19