TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 352

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

Use internal signal
Use internal signal
(Internal) BUSRQ
to CPU (Interrupt)
DVM disable
DVM enable
LD7 to LD0
(8-bit case)
LD7 to LD0
LD7 to LD0
(8 bits)
(8 bits)
LBCD
LBCD
LCP0
LCP0
LCP1
LCP
LFR
LFR
LLP
LLP
LLP
LFR
Condition: FP [9:0] setting = 240 (COM) + 63, LCDDVM<FMN7:0> = 0BH
1
Figure 3.14.7 Detailed Timing Diagram of SR Mode
Figure 3.14.6 Whole Timing Diagram of SR Mode
f
FP
LP1
2
= 78.02 Hz (at <FP9:0> = 120)
Figure 3.14.8 Waveform of LLP, LFR
1-picture display time
3
LP2
Data transmission
t
CP
(1 row data)
N
N
= 2 states
LP3
t
92CH21-350
N + 1
N + 1
STOP
LP10
: Stop time
120
LP11
N + 28
N + 28
1
t
LP
N + 29
N + 29
: LLP cycle
2
t
OPR
LP301 LP302 LP303 LP304
: CPU opration time
3
Note: XT = 1/32768 [s]
1 state = 1/f
Single CP
Double CP
t
LPH
TMP92CH21
120
SYS
2009-06-19
= f
SYS
[s]
1
× 4
2