TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 538

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

ND1ECCRD
ND1FRSTR
ND1FMCR
ND1FDTR
ND1FSPR
ND1FIMR
ND1FISR
Symbol
ND1FSR
(17) NAND flash controller (2/2)
flash reset
flash ECC
flash data
interrupt
interrupt
transfer
Name
register
register
register
register
register
register
register
register
control
NAND
NAND
NAND
NAND
NAND
NAND
NAND
NAND
status
status
strobe
mode
mask
pulse
width
flash
flash
flash
flash
flash
code
Address
1CECH
1CE4H
1CE8H
1CF0H
1CF4H
1CF8H
1CB0H
1D00H
0: Disable
1: Enable
0: Ready
1: Busy
0: Disable
1: Enable
Undefined
write
operation
write
operation
INTEN
BUSY
R/W
WE
D7
D7
7
R
0
0
ECC circuit
11 (at <CE>=X): Reset
00 (at <CE>=1): Disable
01 (at <CE>=1): Enable
10 (at <CE>=1): Read
10 (at <CE>=0): Read ID
ECC data calculated
by NDFC
data
ECC1
D6
D6
6
0
92CH21-536
ECC0
D5
D5
Data window to read/write NAND flash
5
0
Data window to read ECC code
Chip
enable
0: Disable
(
high)
1: Enable
(
low)
NDCE
NDCE
D4
D4
CE
4
0
Undefined
is
is
R/W
R/W
R
Power Control
Always write “11”
PCNT1
SPW3
D3
D3
0
3
0
= f
Pulse width for
SYS
PCNT0
× (This register’s value +1)
SPW2
D2
D2
0
2
0
R/W
NDRE
Address
Latch
Enable
0: Low
1: High
SPW1
ALE
D1
D1
0
1
0
,
TMP92CH21
NDWE
2009-06-19
Reset
controller
1: Change
1: Clear to
Mask for
RDY
Command
Latch
Enable
0: Low
1: High
Read:
Write:
MRDY
SPW0
NDR/ B
“0”
RDY
R/W
RST
R/W
CLE
R/W
D0
D0
0
0
0
0
0
0