TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 149

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TMP92xy21FG

Manufacturer Part Number
TMP92xy21FG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP92xy21FG

Package
LQFP144
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
16
Architecture
32-bit CISC
Usb/spi Channels
-
Uart/sio Channels
2
I2c/sio Bus Channels
-
(s)dram Controller
1
Adc 10-bit Channel
4
Da Converter
-
Timer 8-bit Channel
4
Timer 16-bit Channel
1
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
Y
Number Of I/o Ports
82
Power Supply Voltage(v)
3.0 to 3.6
Address Memory Map
000000H
200000H
400000H
600000H
800000H
C00000H
FFFF00H
FFFFFFH
Figure 3.8.1 Recommended Memory Map for Maximum Specification (Logical address)
Note:
CSZA
Internal I/O, RAM
COMMON-X
COMMON-Y
COMMON-Z
Vector area
(2 Mbytes)
(2 Mbytes)
(2 Mbytes)
(2 Mbytes)
(4 Mbytes)
(4 Mbytes)
LOCAL-X
LOCAL-Y
LOCAL-Z
is a chip select for not only bank 0 to 15 of LOCAL-Z but also COMMON-Z.
Bank 0
Bank 0
Bank 0
64 Mbytes(4 Mbytes × 16)
: Internal area
: Overlapped with COMMON area and disabled setting as LOCAL area.
CSZA
64 Mbytes(2 Mbytes × 32)
1
1
1
92CH21-147
64 Mbytes(2 Mbytes × 32)
SDCS
pin (Note)
2
2
2
3
3
3
ND
ND
or
1
0
CS
CE
CE
CS
3
1
pin (128 Mbytes)
pin (128 Mbytes)
pin
15
15
15
pin
16
CSZB
pin
31
31
31
80
CSZF
pin
Memory controller setting
95
TMP92CH21
CS3 area
CS1 area
CS2 area
2009-06-19
4 Mbytes
4 Mbytes
8 Mbytes
32 Kbytes
CS0 area

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