TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 201

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

USBINTFR4
(07F3H)
bit Symbol
Read/Write
Reset State
Function
Note: The above interrupt can release Halt state from IDLE2 mode. (IDLE1 and STOP mode cannot be released.)
INT_SETUP
R/W
7
0
•
•
•
When read 0: Not generate interrupt
INT_SETUP (Bit7)
INT_EP0 (Bit6)
INT_STAS (Bit5)
control is needed from USB host.
UDC and execute operation according to each request.
Control transfer type - interrupt).
transfer type. If this interrupt occurs during Control write transfer, data
reading from FIFO is needed. If this interrupt occurs during Control read
transfer, transmission data writing to FIFO is needed.
stage. In this case, this interrupt cannot be generated. Therefore, ignore this
interrupt if it occurs after the last packet data has been written in the data
stage because the transmission data number is specified by the host, or it
depends on the capacity of the device.
EP0_STATUS <STAGE_ERR> is set to “1”, and it means that request did not
end normally.
This is the flag register for INT_SETUP (setup - interrupt).
This is set to “1” when the UDC receives a request that S/W (software)
Using S/W (INT_SETUP routine), first read 8-byte device requests from the
This is the flag register for INT_EP0 (received data of the data phase for
In some cases, the host may not assert “ACK” of the last packet in the data
This is the flag register for INT_STAS (status stage end - interrupt).
This is set to “1” when the status stage ends.
If this interrupt is generated, it means that request ended normally.
If this interrupt is not generated and INT_SETUP is generated,
INT_EP0
This is set to “1” when the UDC receives data of the data phase for Control
R/W
6
0
1: Generate interrupt
INT_STAS
R/W
5
0
92CH21-199
INT_STASN
R/W
4
0
When write
INT_EP1N
R/W
3
0
0: Clear flag
1: −
INT_EP2N
R/W
2
0
INT_EP3N
R/W
1
0
TMP92CH21
EP2_Empty_B
2009-06-19
R/W
0
0