TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 368

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

(Notes on settings)
High level width of LLP is adjusted every f
of LLP when transmission speed of the LD bus is set to 2-Clock. LLP is also adjusted every
4-clock of LLP when transmission speed of the LD bus is set to 4-clock of LCP0.
Setting method is the same as in the STN case, following the calculation below.
1. LCP0 cycle: LCP0=f
2. LCP1 cycle: LCP1= f
As indicated above, the cycles of LCP0 and LCP1 are able to set each other.
There are some limitations to settings of LD bus speed and LCDSCC.
Frame correction function is the same as in the STN case.
f
FP
SCC
3. LCP1 Setting: Vertical front porch is determined by LCDCCR0.
BCD
[Hz]
LCP0 cycle is generated by system clock and value of LCDMODE0<SCPW1:0>
High level width of LCP1 is fixed to f
f
LCP1 cycle is generated by value of LCDSCC register.
Vertical back porch is controlled by the pulse number which is <PCPV2:0> subtracted
from LCDFFP<FP9:0> as explained in the SR mode section.
BCD
Vertical front porch is determined by the above 3bits; LCDCCR0<PCPV2:0>.
[Hz] = f
Segment
: Frame frequency (Refresh rate: LBCD cycle)
: FP [9:0] FFP register setting value
: SCC [7:0] LSCC register setting value
Size
SYS
128
160
256
320
64
SYS
SYS
[Hz] / ((SCC+1) × 16 × FP)
× n (n=2, 4, 8: transmission speed of LD bus)
× 16 × (SCC + 1)
Transmission
Speed of
LD bus
92CH21-366
2
4
8
2
4
8
2
4
8
2
4
8
2
4
8
SYS
× 8 cycle. However, LLP is adjusted every 2-clock
SYS
× 4 times. (Positive edge)
Minimum
LCDSCC
value
129
161
17
33
17
33
65
21
41
81
33
65
41
81
9
TMP92CH21
2009-06-19