TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 389

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

SDUUDQM
SDULDQM
SDLUDQM
SDCAS
SDLLDQM
SDRAS
SDWE
SDCS
SDCKE
SDCLK
Note 1: When standby mode is released by a system reset, the I/O registers are initialized and the Self Refresh state is
Note 2: The SDRAM cannot be accessed while it is in the Self Refresh state.
Note 3: To execute the HALT instruction after the Self Refresh Entry command, insert at least 10 bytes of NOP or other
exited. Note that the Auto Refresh function is also disabled at this time.
instructions between the instruction to set SDCMM<SCMM2:0> to “101” and the HALT instruction.
(b) Self-refresh
Self-refresh
to “101”. The self-refresh cycle is shown in Figure 3.16.5. During self-refresh Entry,
refresh is performed within the SDRAM (an auto-refresh command is not needed).
released, following which, refresh is executed according to the setting of the auto-
refresh command.
entry
The self-refresh ENTRY command is generated by setting SDCMM<SCMM2:0>
The auto-refresh command is automatically executed once when self-refresh is
Figure 3.16.5
Timing of Self-Refresh Cycle
92CH21-387
Self-refresh
exit
TMP92CH21
Auto-refresh
2009-06-19