TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 437

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

3.20.4
Note: Since P90 to P91 become high impedance by reset, connect a pull-up or pull-down resistor if necessary.
(Main routine)
(INTI2S interrupt routine)
X: Don't care, −: No change
INTE5I2S
P9CR
P9FC
I2SCTL0
I2SBUFR
I2SCTL0
I2SBUFR
I2SCTL0
(Setting example) Transmitting by SIO mode, I2SCKO = 10 MHz, synchronous with rising edge
Explanation of SIO Mode
(1) Connection example
(2) Procedure
generated.
If <BUSY> = “1” then WAIT else NEXT
Figure 3.20.6 shows an example with external LSI.
A 32-byte FIFO is built-in. If the FIFO’s data becomes empty, an INTI2S interrupt is
In the interrupt routine, write the next transmission data to the FIFO.
The following shows a setting example and timing diagram.
TMP92CH21
(Transmitter)
** ** ** ** ** ** ** **
** ** ** ** ** ** ** **
X
7
−
−
0
−
1
−
1
−
P90/I2SCKO
P91/I2SDO
0
6
−
−
1
1
1
1
1
1
(at f
Figure 3.20.6 Example with External LSI
5
0
−
−
−
−
−
−
−
−
SYS
Port
4
1
−
−
1
1
1
1
1
1
= 20 MHz)
X
3
−
−
0
0
0
0
0
0
2
−
−
−
0
0
0
0
0
0
92CH21-435
1
−
0
1
1
0
1
0
1
0
Example: Shift register
SCK
SI
RCK
0
−
0
1
−
1
−
1
−
1
(Receiver)
Set interrupts level.
Set pins to P90 (I2SCKO) and P91 (I2SDO).
Set SIO mode, LSB first, 8 bits, f
Set rising edge.
Write 32-byte data to FIFO (16 times).
Start transmitting.
Write 32-byte data to FIFO (16 times).
Confirm termination of the 32-byte data transfer.
Start transmitting.
SYS
/2 clocks.
TMP92CH21
2009-06-19