TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 4

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

(9) USB (universal serial bus) controller: 1 channel
(10) I
(11) LCD controller
(12) SDRAM controller: 1 channel
(13) Timer for real-time clock (RTC)
(14) Key-on wakeup (Interrupt key input)
(15) 10-bit AD converter: 4 channels
(16) Touch screen interface
(17) Watchdog timer
(18) Melody/alarm generator
(19) MMU
(20) Interrupts: 50 interrupt
(21) Input/output ports: 82 pins (Except Data bus (16bit), Address bus (24bit) and
(22) NAND flash interface: 2 channels
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
2
S (Inter-IC sound) interface: 1 channel
Compliant with USB ver.1.1
Full-speed (12 Mbps) (Low-speed is not supported.)
Endpoints spec
Endpoint 0: Control 64 bytes* 1-FIFO
Endpoint 1: BULK (out) 64 bytes* 2-FIFO
Endpoint 2: BULK (in) 64 bytes* 2-FIFO
Endpoint 3: Interrupt (in) 8 bytes* 1-FIFO
Descriptor RAM: 384 bytes
I
32-byte FIFO buffer
Supports up to 4096 color for TFT, 256 color, 16, 8, 4 gray levels and B/W for STN
Shift register/built-in RAM LCD driver
Supports 16 M, 64 M, 128 M, 256 M, and up to 512-Mbit SDR (Single Data Rate)-SDRAM
Possible to execute instruction on SDRAM
Available to reduce external components
Melody: Output of clock 4 to 5461 Hz
Alarm: Output of 8 kinds of alarm pattern and 5 kinds of interval interrupt
Expandable up to 512 Mbytes (3 local area/8 bank method)
Independent bank for each program, read data, write data and LCD display data
9 CPU interrupts:
34 internal interrupts: Seven selectable priority levels
7 external interrupts: Seven selectable priority levels (6-edge selectable)
Direct NAND flash connection capability
ECC calculation (for SLC- type)
2
S bus mode/SIO mode selectable (Master, transmission only)
Software interrupt instruction and illegal instruction
92CH21-2
RD
TMP92CH21
2009-06-19
pin)