upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 149
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upd70f3422gj-gae-qs-ax
Manufacturer Part Number
upd70f3422gj-gae-qs-ax
Description
32-bit Single-chip Microcontroller
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.UPD70F3422GJ-GAE-QS-AX.pdf
(930 pages)
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Clock Generator
Bit position
2 to 0
Initial Value
Table 4-12
Address
Access
VBSPS[2:0] SSCG clock divider selection for generating VBCLK:
Bit name
Note
(4)
SCPS - SSCG post scaler control register
The 8-bit SCPS register controls the two independent SSCG post scalers
(frequency dividers) for the CPU system clock VBCLK.
This register can be read/written in 8-bit or 1-bit units.
FFFF F830
21
a)
SCPS register contents
This register can only be written when the SSCG enable bit CKC.SCEN is
cleared (SSCG switched off).
Preliminary User’s Manual U17566EE1V2UM00
Function
H
R/W
. The register is initialized by any reset.
7
0
These bits must not be altered.
VBSPS2
0
0
0
0
1
1
1
1
H
.
R/W
0
6
a
VBSPS1
0
0
1
1
0
0
1
1
R/W
1
5
a
VBSPS0
0
1
0
1
0
1
0
1
R/W
0
4
a
Clock divider setting
VBCLK = SSCG out frequency / 1
VBCLK = SSCG out frequency / 2
VBCLK = SSCG out frequency / 3
VBCLK = SSCG out frequency / 4
not supported
VBCLK = SSCG out frequency / 6
not supported
VBCLK = SSCG out frequency / 8
R/W
3
0
VBSPS2
R/W
2
VBSPS1
R/W
1
Chapter 4
VBSPS0
R/W
0
149
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