upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 94

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 2
94
Filter operation
Initial Value
Input terminal
Filter output
Figure 2-6
Table 2-53
Address
Access
(1)
The input terminal signal is sampled with the sampling frequency f
shorter than 2 sampling cycles are suppressed and no internal signal is
generated. Pulses longer than 3 sampling cycles are recognized as valid
pulses and an internal signal is generated. For pulses between 2 and 3
sampling cycles, the behaviour is not defined. The filter operation is illustrated
in Figure 2-6.
Digital noise removal example
The minimum input terminal pulse width to be validated is defined by the
sampling frequency f
Digital noise removal features
The digital filter function can be individually enabled for each of the
aforementioned external input signals. The filter is enabled/disabled by the
16-bit registers DFEN0 and DFEN1.
DFEN0 - Digital filter enable register
The 16-bit DFEN0 register enables/disables the digital filter for TMP0 to TMP3
and TMG0 input channels and for CSIB0 to CSIB2 input channels.
This register can be read/written in 16-bit, 8-bit and 1-bit units.
FFFF F710
0000
Preliminary User’s Manual U17566EE1V2UM00
DFENC15 DFENC14 DFENC13 DFENC12 DFENC11 DFENC10 DFENC9 DFENC8
DFENC7 DFENC6 DFENC5 DFENC4 DFENC3 DFENC2 DFENC1 DFENC0
Sampling frequency
f
16 MHz (PLL enabled)
4 MHz (PLL disabled)
s
R/W
R/W
= PCLK0
15
7
H
. This register is cleared by any reset.
H
R/W
R/W
14
6
s
. The sampling frequency f
R/W
R/W
13
5
Minimum pulse width to
generate an internal signal
0.125 – 0.1875 µsec
0.5 – 0.75 µsec
R/W
R/W
12
4
R/W
R/W
11
3
s
is PCLK0.
R/W
R/W
10
2
R/W
R/W
Pin Functions
9
1
s
. Spikes
R/W
R/W
8
0