upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 802

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 21
802
Bit position
1 to 0
7
4
3
2
Initial Value
Table 21-4
Address
Access
Bit name
DIR[1:0]
AOUT
ADB1
ADB0
TEN
(5)
MCMPCnk - Compare control registers (k = 1 to 6)
The 8-bit MCMPCnk registers control the operation of the corresponding
compare registers and the output direction of the PWM pin.
These registers can be read/written in 8-bit units.
<base> + A
00
a)
b)
MCMPCnk register contents
Preliminary User’s Manual U17566EE1V2UM00
AOUT
H
Function
Selects the output pins for sine and cosine signals
Transfer enable control bit
Note: This bit functions as a control bit and status flag. It is automatically reset to
Sets 1-bit addition function for cosine side
Sets 1-bit addition function for sine side
Selects the output pins for the PWM signals.
Bits DIR1 and DIR0 address the quadrant to be activated by sine and cosine. The
PWM signal is routed to the specific pin with respect to the sin/cos of each
quadrant.
At the other output pins, the output level is SMV
Note: These bits are only considered if bit AOUT is set to 0.
R/W
. This register is cleared by any reset.
0: The PWM signals for sine and cosine side are output to those pins that are
1: The PWM signal for the sine side is output to pins SMk1 and SMk2. The PWM
0: MCMPnk0/MCMPnk1 master-to-slave register copy is disabled. New data can
1: MCMPnk0/MCMPnk1 master-to-slave register copy is enabled. The copy
0: no 1-bit addition to PWM signal
1: 1-bit addition to PWM signal
0: no 1-bit addition to PWM signal
1: 1-bit addition to PWM signal
7
Do not change this bit.
This bit may be written, but writing is ignored.
DIR1
selected by bits DIR0 and DIR1. At all other pins, the output signal is 0 (SMV
level).
signal for the cosine side is output to pins SMk3 and SMk4.
be written to compare registers MCMPnk0 or MCMPnk1.
process will take place when CNT0 or CNT1, respectively, overflows. Don't
write to compare registers MCMPnk0 or MCMPnk1 while MCMPCnk.TEN = 1.
0
0
1
1
zero upon the next timer counter overflow.
H
R/W
, C
0
6
a
DIR0
H
, E
0
1
0
1
H
, 10
0
R
5
b
Selected output pins
Quadrant 1: SMk1 (sin +), SMk3 (cos +)
Quadrant 2: SMk1 (sin +), SMk4 (cos –)
Quadrant 3: SMk2 (sin –), SMk4 (cos –)
Quadrant 4: SMk2 (sin –), SMk3 (cos +)
H
, 1A
Stepper Motor Controller/Driver (Stepper-C/D)
H
, 1C
TEN
R/W
4
H
ADB1
R/W
3
SS
.
ADB0
R/W
2
DIR1
R/W
1
DIR0
R/W
0
SS