upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 32

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upd70f3422gj-gae-qs-ax

Manufacturer Part Number
upd70f3422gj-gae-qs-ax
Description
32-bit Single-chip Microcontroller
Manufacturer
Renesas Electronics Corporation.
Datasheet
Chapter 1
32
Serial Interfaces
Timers
Control Interfaces
SCKB0, SCKB1, SCKB2
SOB0, SOB1, SOB2
Figure 1-2
VCMPO0, VCMPO1
TOG01 to TOG04
TOG11 to TOG14
TOG21 to TOG24
SIB0, SIB1, SIB2
VCMP0, VCMP1
SM11 to SM14
SM21 to SM24
SM31 to SM34
SM41 to SM44
SM51 to SM54
SM61 to SM64
CRXD0, CRXD1
INTP0 to INTP7
RXDA0, RXDA1
CTXD0, CTXD1
TIG01 to TIG04
TIG11 to TIG14
TIG20 to TIG25
TXDA0, TXDA1
TOP00, TOP01
TOP20, TOP21
TOP30, TOP31
DBD0 to DBD7
TOP10, TOP11
SDA0, SDA1
TIP00, TIP01
TIP10, TIP11
TIP20, TIP21
TIP30, TIP31
SCL0, SCL1
ANI0-ANI15
SGO/SGOF
DBWR
SGOA
DBRD
NMI
Figure 1-2 provides a functional block diagram of the V850E/DL3 µPD70F3427
microcontroller.
V850E/DL3 µPD70F3427 block diagram
Preliminary User’s Manual U17566EE1V2UM00
TMP0 - TMP3
LCD Bus I/F
TMG0 - TMG2
Comparator
2 x UARTA
10-bit ADC
2 x Voltage
16-bit Timer
Generator
16-bit Timer
Controller
3 x CSIB
channels
2 x CAN
Stepper
Interrupt
2 x I
Sound
Motor
C/D
16
2
C
BRG
BRG
Reset
TMZ0 - TMZ9
16-bit Timer
16-bit Timer
16-bit Timer
Watchdog
Timer
WCT
WT
On-Chip Debug Unit
Standby Controller
System Controller
POC
CPU Core
Watch
and
Watch Correction
Timer
NPB (NEC Peripheral Bus)
Power and Reset
Power supply
CPU
Correction
ROM
RAM
DMA
Ports
Clock Generator
Spread Spectrum PLL
Sub oscillator
Ring oscillator
Main oscillator
Sub oscillator
Supervision
Main and
debug I/F
N-Wire
PLL
Control
Unit
Bus
Bridge
Bus
Flash
XT1
XT2
RESET
FOUT
FOUT
DMS
DRST
DDI
DDO
DCK
X1
X2
Auxiliary Functions
Controller
Memory
Clock Generator
Memory
Introduction
D0 to D15
D16 to D31
CS0, CS1
CS3, CS4
BE3 to BE0
RD
WR
WAIT
BCLK
A0 to A23

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