upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 620

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 18
620
18.10 Error Detection
18.9 Address Match Detection Method
Note
(4)
(5)
Wait cancellation method
The four wait cancellation methods are as follows.
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•
•
•
Master only
When an 8-clock wait has been selected (WTIMn bit = 0), the output level of
the ACK signal must be determined prior to wait cancellation.
Stop condition detection
The INTIICn signal is generated when a stop condition is detected.
In I
transmitting the corresponding slave address.
Address match detection is performed automatically by hardware. The INTIICn
signal occurs when a local address has been set to the SVAn register and
when the address set to the SVAn register matches the slave address sent by
the master device, or when an extension code has been received.
In I
transmission is captured by the IICn register of the transmitting device, so the
data of the IICn register prior to transmission can be compared with the
transmitted IICn data to enable detection of transmission errors. A
transmission error is judged as having occurred when the compared data
values do not match.
Preliminary User’s Manual U17566EE1V2UM00
2
2
By setting the IICCn.WRELn bit to 1
By writing to the IICn register
By start condition setting (IICCn.STTn bit = 1)
By stop condition setting (IICCn.SPTn bit = 1)
C bus mode, the master device can select a particular slave device by
C bus mode, the status of the serial data bus pin (SDAn) during data
Note
Note
I
2
C Bus (IIC)