upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 600

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 18
600
Transfer lines
Master (Tx)
Slave (Rx)
Figure 18-12
ACKEn
SDAn
SCLn
SCLn
SCLn
IICn
IICn
(2)
H
When master and slave devices both have a nine-clock wait
(master: transmission, slave: reception, and ACKEn bit = 1)
Wait signal (2/2)
A wait may be automatically generated depending on the setting of the
IICCn.WTIMn bit.
Normally, when the IICCn.WRELn bit is set to 1 or when FFH is written to the
IICn register on the receiving side, the wait status is cancelled and the
transmitting side writes data to the IICn register to cancel the wait status.
The master device can also cancel its own wait status via either of the following
methods.
• By setting the IICCn.STTn bit to 1
• By setting the IICCn.SPTn bit to 1
Preliminary User’s Manual U17566EE1V2UM00
Output according to previously set ACKEn bit value
D2
6
6
D1
7
7
Master and slave both wait
after output of ninth clock.
D0
8
8
ACK
9
9
Wait signal
from master
/slave
IICn data write (cancel wait)
Wait signal
from slave
1
D7
FFH is written to IICn register
or WRELn bit is set to 1.
1
D6
2
2
D5
3
3
I
2
C Bus (IIC)