upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 172

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 4
172
Table 4-27
(4)
Sub-WATCH mode
In Sub-WATCH mode, the clock supply for the CPU and the majority of
peripherals is stopped. Main oscillator, PLL, and SSCG are stopped. By
default, ring oscillator and sub oscillator operation is not influenced. For
exceptions see “Ring and sub oscillator operation” on page 184.
Clock Generator status in Sub-WATCH mode
The Sub-WATCH mode can be released by
• the unmasked maskable interrupts INTPn, INTCnWUP, INTWTnUV,
• NMI0, NMIWDT
• RESET, RESPOC, RESWDT, RESCMM, RESCMS
On Sub-WATCH mode release, the CPU starts operation using the following
clocks:
• if PSM.OSCDIS = 1: sub clock source selected before Sub-WATCH mode
• if PSM.OSCDIS = 0: main oscillator
If the ring oscillator was stopped before entering the Sub-WATCH mode, the
oscillation stabilization time for the ring oscillator is ensured by hardware after
Sub-WATCH release.
PLL and SSCG remain stopped after Sub-WATCH release.
Peripheral clock supply is switched to main oscillator supply, if
PSM.OSCDIS = 0, otherwise the ring oscillator is used for peripheral clocks.
Preliminary User’s Manual U17566EE1V2UM00
Item
Main oscillator
Sub oscillator
Ring oscillator
SSCG
PLL
VBCLK (CPU system)
IICLK
PCLK0, PCLK1
PCLK2…PCLK15
SPCLK0, SPCLK1
SPCLK2…SPCLK15
FOUTCLK
WTCLK / LCDCLK
WDTCLK
WCTCLK
INTVCn, INTCBnR
was entered, that means, either ring oscillator or sub oscillator (defined by
PCC.SOSCP)
Status
unchanged/stopped
operates
operates/stopped
stopped
stopped
stopped
stopped
stopped
stopped
stopped
stopped
unchanged
unchanged
unchanged/stopped
stopped
Stopped if PSM.OSCDIS = 1
Stopped if WCC.ROSTP = 1
Remarks
Stopped, if the selected clock source
stops
Stopped, if the selected clock source
stops
Stopped, if the selected clock source
stops
Clock Generator