upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 463

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

16-bit Multi-Purpose Timer G (TMG)
Chapter 13
(b) Example: Capture where both edges of TIGnm are valid (match and
clear)
For the timing chart TMGn0 is selected as the counter corresponding to
TOGn1, and 0FFFH is set in GCCn0.
t
f
COUNTx
D3
TMGn0
0000H 0001H
D0
D1
0FF F H 0000H
D2
C ount start
Cl ear
TIGn1
GCCn1
D0
D1
D2
D3
INTTGnCC1
INTTGnCC0
CCFG1
No "match and cl ea r"
"Match and c lea r"
No "match and cl ea r"
Figure 13-12
Timing when both edges of TIGnm are valid (match and clear)
Note
The figure above shows an image. In actual circuitry, 3 to 4 periods of the
count-up signal (f
) are required from the input of a waveform to TOGn1
COUNT
until a capture interrupt is output. (See Figure 13-4 on page 454.)
Caution
If two or more match and clear events occur between captures, a software-
based measure needs to be taken to count INTCCGn0 or INTCCGn5.
(c) When 0000H is set in GCCn0 or GCCn5 (match and clear)
When 0000H is set in GCCn0 (GCCn5), the value of the counter is fixed at
0000H, and does not operate. Moreover, INTCCGn0 (INTCCGn5) continues to
be active.
(d) When FFFFH is set in GCCn0 or GCCn5 (match and clear)
When FFFFH is set in GCCn0 (GCCn5), operation equivalent to the free-run
mode is performed. When an overflow occurs, INTTMGn0 (INTTMGn1) is
generated, but INTCCGn0 (INTCCGn5) is not generated.
Preliminary User’s Manual U17566EE1V2UM00
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