upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 836

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 23
836
LBCTL0.BYF0
LBCTL0.TPF0
LBDATA0
DBD[7:0]
INTLCD
write buffer
SPCLK
DBWR
DBRD
internal
Figure 23-4
Sequence
Note
Write 1
(2)
st
1
halfword to LBDATA0 register
st
halfword (consists of byte0 and byte1)
3. All four bytes of the word are transferred back-to-back via the external bus
4. After the transfer on the external bus interface has been completed, the
Writing halfwords
Writing a halfword transmits two bytes to the external LCD Controller/Driver.
Timing (mod80: LBTCTL0.IMD0 = 0): write consecutive halfwords,
LBWST0.WST0 = 5, LBCYC0.CYC0 = 8, LBTCTL0.TCIS0 = 0
The timing diagrams are for functional explanation purposes only without any
relevance to the real hardware implementation.
1. The first halfword of LCD data is written to the LBDATA0 register. The
2. The LBDATA0 register contents is copied to the write buffer. This clears
3. Caused by the interrupt, the DMA writes a second halfword to LBDATA0.
4. Because the transfer (two bytes) on the external bus interface is still going
5. After the transfer over the external bus interface has been completed, the
Filling the write buffer starts a new transfer to the external LCD controller.
Preliminary User’s Manual U17566EE1V2UM00
interface.
LBCTL0.TPF0 is cleared.
internal bus transfer takes some clocks until the interface register is written.
Then the busy flag LBCTL0.BYF0 is set until the data is copied to the write
buffer.
LBCTL0.BYF0 and causes the interrupt output to become active for one
clock cycle. Transfer on the external bus interface starts with byte 0. The
flag LBCTL0.TPF0 is set to indicate that a transfer is in progress.
The CPU can write this halfword as well after it has checked the busy flag
LBCTL0.BYF0. The internal bus transfer again takes some clock cycles
until the LBDATA0 register is written and LBCTL0.BYF0 is set.
on and the LBDATA0 register contents can not be copied to the write buffer
immediately, LBCTL0.BYF0 is set.
write buffer is filled with the contents of LBDATA0. The busy flag
LBCTL0.BYF0 is cleared, and the interrupt output INTLCD becomes active
for one clock cycle.
Byte0
Write 2
1
st
halfword
nd
halfword to LBDATA0 register
Byte1
2
nd
halfword (consists of byte0 and byte1)
Byte0
2
nd
halfword
LCD Bus Interface (LCD-I/F)
Byte1