upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 626

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 18
626
Figure 18-15
18.15.2 Master operation 2
IICEn = SPIEn = WTIMn = 1
Start IICn write transfer
Start IICn write transfer
Data processing
IICCLn
IICBSYn = 0?
IICCn
The following shows the flowchart for master communication when the
communication reservation function is disabled (IICRSVn bit = 1) and the
master operation is started without detecting a stop condition
(STCENn bit = 1).
IICFn
Master operation flowchart (2)
Preliminary User’s Manual U17566EE1V2UM00
STCFn = 0?
INTIICn = 1?
INTIICn = 1?
ACKDn = 1?
ACKDn = 1?
TRCn = 1?
Insert wait
STTn = 1
START
←
←
←
Yes
Yes
Yes (address transfer completion)
Yes
Yes (transmit)
Yes
Yes
××H
××H
××H
No
No
No
No
No
(restart)
No (receive)
Transfer clock selection
IICFn register setting
IICCn register initial setting
Wait time is secured by software
(see Table 17-7)
No
Generate stop condition
Reception completed?
Transfer completed?
Data processing
Start reception
INTIICn = 1?
WRELn = 1
WTIMn = 0
ACKEn = 1
ACKEn = 0
SPTn = 1
End
Yes
Yes
Yes
Stop master communication
No
No
(no slave with matching address)
Generate stop condition
Master communication is
stopped because bus is occupied
End
I
2
C Bus (IIC)