upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 483

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Watch Timer (WT)
Initial Value
Initial Value
Address
Address
Access
Access
Note
Note
(2)
(3)
WTnCNT0 - WTn synchronized counter register
The WTnCNT0 register is the synchronized register that can be used to read
the present value of the 16-bit counter.
“Synchronized” means that the read access via the internal bus is
synchronized with the counter clock. The synchronization process causes a
delay, but the resulting value is reliable.
This register is read-only, in 16-bit units.
<base> of WTn
0000
Due to the low frequencies of the counter clocks, the synchronization can take
about up to two WTCLK. For a quick response, it is recommended to read the
non-synchronized counter register WTnCNT1.
WTnCNT1 - WTn non-synchronized counter read register
The WTnCNT1 register is the non-synchronized register that can be used to
read the present value of the corresponding 16-bit counter.
“Non-synchronized” means that the read access via the internal bus is not
synchronized with the counter clock. It returns the instantaneous value
immediately, with the risk that this value is just being updated by the counter
and therefore in doubt.
This register is read-only, in 16-bit units.
<base> + 2
0000
The value read from this register can be incorrect, because the read access is
not synchronized with the counter clock.
Therefore, this register shall be read multiple times within one period of the
counter clock cycle.
If the difference between the first and the second value is not greater than one,
you can consider the second value to be correct. If the difference between the
two values is greater than one, you have to read the register a third time and
compare the third value with the second. Again, the difference must not be
greater than one.
If the read accesses do not happen within one period of the counter clock
cycle, the difference between the last two values will be greater than one. In
this case, you can only repeat the procedure or estimate the updated counter
value.
Preliminary User’s Manual U17566EE1V2UM00
15
15
H
H
14
14
. This register is cleared by any reset and when WTnCTL.WTCE = 0.
. This register is cleared by any reset and when WTnCTL.WTCE = 0.
13
13
H
12
12
Instantaneous counter value (non-synchronized)
11
11
Updated counter value (synchronized)
10
10
9
9
8
8
R
R
7
7
6
6
5
5
4
4
3
3
2
2
Chapter 14
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