upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 229

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upd70f3422gj-gae-qs-ax

Manufacturer Part Number
upd70f3422gj-gae-qs-ax
Description
32-bit Single-chip Microcontroller
Manufacturer
Renesas Electronics Corporation.
Datasheet
Features summary
Chapter 6 Flash Memory
6.1 Overview
Preliminary User’s Manual U17566EE1V2UM00
The µPD70F3420, µPD70F3421, µPD70F3422, µPD70F3422, µPD70F3423,
µPD70F3424, µPD70F3425, µPD70F3426 and µPD70F3427 microcontrollers
are equipped with internal flash memory. The flash memory is attached to the
V850 Fetch Bus VFB interface of the V850E CPU core. It is used for program
code and storage of constant data.
When fetching an instruction, 4 bytes of the flash memory can be accessed in
1 clock.
The flash memory can be written mounted on the target board (on-board
write), by connecting a dedicated flash programmer to the target system.
Flash memory is commonly used in the following development environments
and applications:
• For altering software after solder-mounting of the microcontroller on the
• For differentiating software in small-scale production of various models.
• For data adjustment when starting mass production.
• Internal VFB flash memory:
• µPD70F3427, µPD70F3426, µPD70F3425, µPD70F3424 operation speed:
• µPD70F3423 operation speed:
• µPD70F3422, µPD70F3421, µPD70F3420 operation speed:
• All-blocks batch erase or single block erase
• Erase/write with single power supply
• Communication with dedicated flash programmer via various serial
• On-board and off-board programming
• Flash memory programming by self-programming
target system.
– µPD70F3427, µPD70F3426, µPD70F3425: 1 MB
– µPD70F3424, µPD70F3423: 512 KB
– µPD70F3422: 384 KB
– µPD70F3421: 256 KB
– µPD70F3420: 128 KB
up to 50.4 MHz by 2-way interleaved access
– 4-byte/1 CPU clock cycle access for consecutive instruction fetches
– 4-byte/5 CPU clock cycles access for random instruction and data fetches
up to 25.2 MHz by 2-way interleaved access
– 4-byte/1 CPU clock cycle access for consecutive instruction fetches
– 4-byte/3 CPU clock cycles access for random instruction and data fetches
up to 25.2 MHz with non-interleaved access
interfaces
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