upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 330

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Chapter 8
330
DMA Transfer
DMA Transfer
Request CH2
Request CH3
DMA Transfer
DMA Transfer
DMA Transfer
Request CH2
Request CH3
Request CH0
Figure 8-8
Figure 8-9
CPU
8.12.2 Block transfer mode
CPU
Note
CPU
DMA3
Note
CPU DMA3 CPU
CPU DMA3 DMA3
Figure 8-8 shows a single transfer mode example in which two or more lower
priority DMA transfer requests are generated within one clock after the end of a
single transfer. DMA channels 0, 2 and 3 are used for this single transfer
example. When three or more DMA transfer request signals are activated at
the same time always the two highest priority DMA transfers are performed
alternately.
Single transfer example 4
The bus is always released
In the block transfer mode, once transfer begins, the DMAC continues the
transfer operation without releasing the bus until a terminal count occurs. No
other DMA requests are acknowledged during block transfer.
After the block transfer ends and the DMAC releases the bus and another DMA
transfer can be acknowledged.
Figure 8-9 shows a block transfer mode example. It is a block transfer mode
example in which a higher priority DMA transfer request is generated. DMA
channels 2 and 3 are used for the block transfer example.
Block transfer example
Preliminary User’s Manual U17566EE1V2UM00
Note
DMA2
Note
CPU
DMA3
DMA0 CPU
DMA3
Note
DMA2 CPU
DMA3 DMA3
Note
DMA channel 0
terminal count
DMA0
DMA3
Note
CPU
DMA channel 3
terminal count
DMA2 CPU
DMA3
Note
CPU
DMA3 CPU DMA2 CPU
The bus is always released
DMA2 DMA2 DMA2
Note
DMA channel 2
terminal count
DMA Controller (DMAC)
Note
DMA channel 3
terminal count
DMA3
DMA2 DMA2
CPU
CPU