upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 539
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upd70f3422gj-gae-qs-ax
Manufacturer Part Number
upd70f3422gj-gae-qs-ax
Description
32-bit Single-chip Microcontroller
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.UPD70F3422GJ-GAE-QS-AX.pdf
(930 pages)
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Asynchronous Serial Interface (UARTA)
Division ratio (k)
4
8
20
50
100
255
Table 16-10
Note
Maximum allowable baud rate error
+2.32%
+3.52%
+4.26%
+4.56%
+4.66%
+4.72%
Therefore, the minimum baud rate that can be received by the destination is as
follows.
Obtaining the allowable baud rate error for UARTAn and the destination from
the above-described equations for obtaining the minimum and maximum baud
rate values yields the following.
Maximum/Minimum allowable baud rate error
1.
2.
Preliminary User’s Manual U17566EE1V2UM00
The reception accuracy depends on the bit count in 1 frame, the input clock
frequency, and the division ratio (k). The higher the input clock frequency
and the larger the division ratio (k), the higher the accuracy.
k: Setting value of UAnCTL2.UAnBRS[7:0]
BRmin
=
(
FLmax 11
⁄
)
–
1
=
------------------ -
21k 2
20k
–
×
Brate
Minimum allowable baud rate error
-2.43%
-3.61%
-4.30%
-4.58%
-4.67%
-4.72%
Chapter 16
539
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