upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 583

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

I
2
Condition for clearing (MSTSn = 0)
• When a stop condition is detected
• When the ALDn = 1 (arbitration loss)
• Cleared by LRELn = 1 (communication save)
• When the IICEn bit changes from 1 to 0 (operation
• After reset
Condition for clearing (ALDn = 0)
• Automatically cleared after the IICSn register is
• When the IICEn bit changes from 1 to 0 (operation
• After reset
Condition for clearing (EXCn = 0)
• When a start condition is detected
• When a stop condition is detected
• Cleared by LRELn = 1 (communication save)
• When the IICEn bit changes from 1 to 0 (operation
• After reset
C Bus (IIC)
MSTSn
stop)
ALDn
read
stop)
EXCn
stop)
0
1
0
1
0
1
Note
Initial Value
Address
Slave device status or communication stand-by status
Master device communication status
This status means either that there was no arbitration or that the arbitration result was a “win”.
This status indicates the arbitration result was a “loss”. The MSTSn bit is cleared.
Extension code was not received.
Extension code was received.
Access
Note
(2)
IICSn - IICn status registers
The IICSn registers indicate the status of the I
This register can only be read in 8-bit or 1-bit units.
<base> + 6
00
Any bit manipulation instruction targetting this register also clears this bit.
Preliminary User’s Manual U17566EE1V2UM00
MSTSn
H
. This register is cleared by any reset.
R
7
H
ALDn
R
6
Detection of extension code reception
Arbitration loss detection
EXCn
Master device status
R
5
Condition for setting (EXCn = 1)
•
Condition for setting (MSTSn = 1)
• When a start condition is generated
Condition for setting (ALDn = 1)
• When the arbitration result is a “loss”.
data are either “0000” or “1111” (set at the rising
edge of the eighth clock).
When the higher four bits of the received address
COIn
R
4
TRCn
R
3
2
Cn bus.
ACKDn
R
2
STDn
R
1
Chapter 18
SPDn
R
0
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