upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 417
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upd70f3422gj-gae-qs-ax
Manufacturer Part Number
upd70f3422gj-gae-qs-ax
Description
32-bit Single-chip Microcontroller
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.UPD70F3422GJ-GAE-QS-AX.pdf
(930 pages)
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16-bit Timer/Event Counter P (TMP)
Figure 11-35
TPnCCRm register
INTTPnOV signal
TIPnm pin input
16-bit counter
TPnOVF bit
TPnCE bit
FFFFH
0000H
(d) Processing of overflow if capture trigger interval is long
Example of incorrect processing when capture trigger interval is long
Preliminary User’s Manual U17566EE1V2UM00
If the pulse width is greater than one cycle of the 16-bit counter, care must
be exercised because an overflow may occur more than once from the first
capture trigger to the next. First, an example of incorrect processing is
shown below.
The following problem may occur when long pulse width is measured in the
free-running timer mode.
<1> Read the TPnCCRm register (setting of the default value of the
<2> An overflow occurs. Nothing is done by software.
<3> An overflow occurs a second time. Nothing is done by software.
<4> Read the TPnCCRm register.
TIPnm pin input).
Read the overflow flag. If the overflow flag is 1, clear it to 0.
Because the overflow flag is 1, the pulse width can be calculated by
(10000H + D
Actually, the pulse width must be (20000H + D
overflow occurs twice.
m1
- D
D
m0
<1> <2>
m0
) (incorrect).
1 cycle of 16-bit counter
Pulse width
D
m0
<3> <4>
m1
D
m1
- D
m0
D
m1
) because an
Chapter 11
417
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