upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 255

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Bus and Memory Control (BCU, MEMC)
Table 7-3
7.2.2 Chips select priority control
7.2.3 Peripheral I/O area
Note
(1)
The chip select signals CS0 to CS7 can be assigned to overlapping memory
areas by setting the chip select area control registers CSC0 and CSC1. The
chip select priority control rules the generation of chip select signals in this
case.
Access to internal resources, which are concurrently mapped to an external
memory areas overrules the external access. As a consequence, the assigned
CSn signal is not generated externally.
If different chip select signals are set (CSC0.CSCkm = 1) for the same memory
bank, the priority order is as follows:
• internal resources > CS0 > CS2 > CS1 > CS3
• internal resources > CS7 > CS5 > CS6 > CS4
Examples:
• If both chip select signal CS0 and CS1 are set for memory bank 2, only the
• If during access to bank 2 CS2 should not be active, activate CS0 for this
Two areas of the address range are reserved for the registers of the on-chip
peripheral functions. These areas are called “peripheral I/O areas”:
Peripheral I/O areas
Fixed peripheral I/O area
The fixed peripheral I/O area holds the registers of the on-chip peripheral I/O
functions.
Because the address space covers 64 MB, the address bits A[31:26] are not
considered. Therefore, in this manual, all addresses of peripheral I/O registers
in the 4 KB peripheral I/O area are given in the range FFFF F000
FFFF FFFF
Preliminary User’s Manual U17566EE1V2UM00
Name
Fixed peripheral I/O area
Programmable peripheral
I/O area (PPA)
chip select signal CS0 will be generated.
bank (CSC0.CS02 = 1). Due to the priority order, only chip select signal
CS0 will be active for bank 2.
H
instead of 03FF F000
Address range
03FF F000
Can be allocated at arbitrary addresses.
Base address is defined in the BPC register.
H
H
to 03FF FFFF
to 03FF FFFF
H
H
.
H
to
Chapter 7
Size
4 KB
16 KB
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