upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 729

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

CAN Controller (CAN)
Caution
(2)
(3)
Status in CAN sleep mode
The CAN module is in one of the following states after it enters the CAN sleep
mode:
• The internal operating clock is stopped and the power consumption is
• The function to detect the falling edge of the CAN reception pin (CRXDn)
• To wake up the CAN module from the CPU, data can be written to the
• The CANn module registers can be read, except for the CnLIPT, CnRGPT,
• The CANn message buffer registers cannot be written or read.
• A request for transition to the initialization mode is not acknowledged and is
Releasing CAN sleep mode
The CAN sleep mode is released by the following events:
• When the CPU writes 00B to the PSMODE1 and PSMODE0 bits
• A falling edge at the CAN reception pin (CRXDn) (i.e. the CAN bus level
If this falling edge is at the SOF of a receive frame, no receive operation,
including returning ACK, is performed on that frame. No receive operation is
performed on the subsequent frames either, unless the clock is supplied to the
CAN macro.
After releasing the sleep mode, the CAN module returns to the operation mode
from which the CAN sleep mode was requested and the PSMODE1 and
PSMODE0 bits are reset to 00B. If the CAN sleep mode is released by a
change in the CAN bus state, the CnINTS.CINTS5 bit is set to 1, regardless of
the CnIE.CIE bit. After the CAN module is released from the CAN sleep mode,
it participates in the CAN bus again by automatically detecting 11 consecutive
recessive-level bits on the CAN bus.
When a request for transition to the initialization mode is made while the CAN
module is in the CAN sleep mode, that request is ignored; the CPU has to be
released from sleep mode by software first before entering the initialization
mode.
Preliminary User’s Manual U17566EE1V2UM00
minimized.
remains in effect to wake up the CAN module from the CAN bus.
PSMODE1 and PSMODE0 bits, but nothing can be written to other CANn
module registers or bits.
CnLOPT, and CnTGPT registers.
ignored.
shifts from recessive to dominant)
•If a CAN sleep mode request is pending waiting for the CAN bus state to
•If the CAN sleep mode transition request is made while a initialization
become bus idle while the CAN module is in one of the operation
modes, and if a request for transition to the initialization mode is made,
the pending CAN sleep mode request becomes disabled, and only the
initialization mode request is enabled (in this case, the CAN sleep mode
request continues to be held pending).
mode transition request is held pending waiting for completion of
communication in one of the operation modes, the CAN sleep mode
transition request is ignored and only the initialization mode transition
request remains valid (in this case, the CAN sleep mode request
continues to be held pending).
Chapter 19
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