upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 277

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Bus and Memory Control (BCU, MEMC)
R/W
Bit position Bit name Function
15
0
14 to 12
3 to 0
PRW2 PRW1 PRW0
R/W
14
Initial Value
Table 7-24
Address
R/W
Access
PRW[2:0] Page ROM on-page wait control.
13
MA[6:3]
(7)
R/W
12
PRC - Page ROM configuration register
The 16-bit PRC register controls whether a page ROM cycle is on-page or
off-page.
The register specifies the address mask. Masked address bits are not
considered when deciding between on-page or off-page access. Set the mask
according to the number of continuously readable bits.
For page access (cycle is on-page) the register defines the number of inserted
data wait cycles.
This register can be read/written in 16-bit units.
FFFF F49A
7000
PRC register contents
Preliminary User’s Manual U17566EE1V2UM00
Sets the number of data waits corresponding to the internal system clock.
Note: The number of wait states defined in the PRC register is only valid if on-page
Mask address.
Setting bits MA6 to MA3 masks the corresponding addresses A6 to A3.
R/W
MA6 MA5
11
0
0
0
0
0
1
H
PRW[2:0]
access is enabled.
If on-page is disabled, the number of wait states is defined by registers DWC0
and DWC1.
R/W
10
000
001
010
011
111
0
...
0
0
0
1
1
H
B
B
B
B
B
R/W
MA4
9
0
0
0
1
1
1
R/W
Inserted data wait states
No wait state inserted
1 wait state
2 wait states
3 wait states
...
7 wait states
MA3
8
0
0
1
1
1
1
R/W
7
0
LBk[1:0]=00
128 x 8 bits
bus width:
16 x 8 bits
32 x 8 bits
64 x 8 bits
8 x 8 bits
8 bits
R/W
Number of continuously readable bits
6
0
R/W
B
5
0
LBk[1:0]=01
R/W
16 x 16 bits
32 x 16 bits
64 x 16 bits
bus width:
4 x 16 bits
8 x 16 bits
4
0
16 bits
MA6
R/W
3
B
MA5
R/W
2
LBk[1:0]=10
16 x 32 bits
32 x 32 bits
bus width:
2 x 32 bits
4 x 32 bits
8 x 32 bits
32 bits
MA4
R/W
Chapter 7
1
MA3
R/W
B
0
277