upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 839

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

LCD Bus Interface (LCD-I/F)
LBCTL0.BYF0
LBCTL0.TPF0
DBWR(R/W)
LBDATA0
LBCTL .EL=0
LBCTL .EL=1
DBRD(E)
DBRD(E)
DBD[7:0]
INTLCD
SPCLK
Figure 23-7
Sequence
Note
(2)
Dummy read byte from LBDATA0 register
Reading bytes
The following figure shows a byte read operation in mod68 mode.
Timing (mod68: LBTCTL0.IMD0 = 1): read consecutive bytes,
LBWST0.WST0 = 4, LBCYC0.CYC0 = 7, LBTCTL0.TCIS0 = 0
The timing diagrams are for functional explanation purposes only without any
relevance to the real hardware implementation.
1. A dummy read to the LBDATA0 register starts the transfer of one byte from
2. When the data on the LCD Bus Interface is sampled, LBCTL0.BYF0 is
3. A new read to LBDATA0 is performed while the previous transfer has not
4. Again, the data that has been sampled is available in LBDATA0 and the
5. Steps 2 to 4 are repeated until the last byte to be read has been sampled.
6. The last byte is not read from the LBDATA0 register but from LBDATAR0 in
Preliminary User’s Manual U17566EE1V2UM00
the external LCD controller. The busy flag LBCTL0.BYF0 is set
immediately. The “transfer in progress” flag LBCTL0.TPF0 is set on the
rising edge of the clock.
The data that is read from LBDATA0 belongs to a previous transfer and
may be ignored.
cleared and the data is available in LBDATA0. The interrupt output INTLCD
becomes active for one clock cycle.
been finished (cycle time not elapsed). The busy flag LBCTL0.BYF0 is set
immediately, but the new transfer is started after the previous one is
complete. The “transfer in progress flag” LBCTL0.TPF0 remains set.
The data that is read from LBDATA0 is the first LCD data byte.
busy flag LBCTL0.BYF0 is cleared.
order to avoid a further read transfer on the LCD bus.
1
st
Byte
sample point
1
st
Byte
Read 1
st
byte from LBDATA0 register
2
nd
Byte
Read 2
2
nd
nd
Byte
byte from LBDATA0 register
3
rd
Byte
3
rd
Byte
Read 3
without initiating a new transfer
rd
byte from LBDATA0 R register
Chapter 23
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