upd70f3422gj-gae-qs-ax Renesas Electronics Corporation., upd70f3422gj-gae-qs-ax Datasheet - Page 627

• Manufacturer Part Number: upd70f3422gj-gae-qs-ax
• Description: 32-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

I
2
C Bus (IIC)
Figure 18-16
18.15.3 Slave operation
I
2
C
(1)
(2)
The following shows the processing procedure of the slave operation.
Basically, the operation of the slave device is event-driven. Therefore,
processing by an INTIICn interrupt (processing requiring a significant change
of the operation status, such as stop condition detection during
communication) is necessary.
The following description assumes that data communication does not support
extension codes. Also, it is assumed that the INTIICn interrupt servicing
performs only status change processing and that the actual data
communication is performed during the main processing.
Software outline during slave operation
Therefore, the following three flags are prepared so that the data transfer
processing can be performed by transmitting these flags to the main
processing instead of INTIICn signal.
Communication mode flag
This flag indicates the following communication statuses.
• Clear mode:
• Communication mode
Ready flag
This flag indicates that data communication is enabled. This is the same status
as an INTIICn interrupt during normal data transfer. This flag is set in the
interrupt processing block and cleared in the main processing block. The ready
flag for the first data for transmission is not set in the interrupt processing
block, so the first data is transmitted without clear processing (the address
match is regarded as a request for the next data).
Preliminary User’s Manual U17566EE1V2UM00
Data communication not in progress
Data communication in progress (valid address detection stop condition
detection, ACK signal from master not detected, address mismatch)
INTIICn signal
Setting, etc.
Interrupt servicing
Setting, etc.
Data
Flag
Main processing
Chapter 18
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