80ksbr200 Integrated Device Technology, 80ksbr200 Datasheet

80ksbr200

Manufacturer Part Number

80ksbr200

Description

Srio Serial Buffer Flow-control Device

Manufacturer

Integrated Device Technology

Datasheet

1.80KSBR200.pdf (172 pages)

Current page: 1 of 172
Download datasheet (2Mb)

„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a

Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.

Device Overview

connect to any Serial RapidIO compliant interface. This device is built to

work with any sRIO device and especially with the IDT Pre-Processing

Switch (PPS), IDT70K200. The SerB performs buffering and off-loading

of data as well as buffer-delay of data samples in various environments.

This device primarily acts as an master in which the SerB bursts data to

a programmed memory location once some criteria have been meet.

This combination of storage and flexibility make it the perfect buffering

solution for sRIO systems.

Features

Block Diagram

The IDT80KSBR200 is a high speed Serial Buffer (SerB) that can

–

Serial RapidIO Port

Interface - sRIO

10 Gbps Throughput

18Mbit Internal Density

One four-lane (4x) link, configurable to one-lane (1x) link

Port Speeds selectable: 3.125 Gbps, 2.5 Gbps, or 1.25 Gbps

Short haul or long haul reach for each PHY speed

Support 8-bit and 16-bit deviceID

Error management supports standard

sRIO version 1.3

Class 1+ End Point Device

1x/4x sRIO

Interface

S-Port 1

TCK

TMS

TDO

SDA

TDI

SCL

sRIO SERIAL BUFFER

FLOW-CONTROL DEVICE

Hardwire

Config

Configuration

and

Flag Registers

Flags

Queue 0

18 Mbits

1 of 172

K/K

–

Programmable Target Address

Packet Tally Indicator

Packet Interval Timer

Replace Missing Packet

Optional External QDR SRAM Available

Seamless Integration of Internal and External Memory

Single Port Buffering

Status Flags for Combined Internal/External Memories

Direct or polled operation of flag status bus

Optional Watermark

Interface - I

Interface - JTAG Interface

High-Speed CMOS Technology

Package: 484-pin Plastic Ball Grid Array

Up to 72Mbit external QDR SRAM

QDR SRAM, 200 MHz; (18M, 36M, 72M)

Internal and external memory functions as a single buffer

Full, Empty, Partially Empty, Partially Full

Serial Buffer can Either Send a Flag or Transmit Data at a Specific Packet

Count

One I

JTAG Functionality for boundary scan and programming

1.2V Core operation with 3.3/2.5V JTAG interface

23mm x 23mm, 1.0mm ball pitch

C port for maintenance and error reporting

C Interface Port

Rd Wr

P-Port

drw01 DSC-6730

Advanced Datasheet

PHY Clk

QDR Clk

80KSBR200

March 19, 2007

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