80ksbr200 Integrated Device Technology, 80ksbr200 Datasheet - Page 137

• Manufacturer Part Number: 80ksbr200
• Description: Srio Serial Buffer Flow-control Device
• Manufacturer: Integrated Device Technology

„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a
Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Notes
15.4.1 Boundary Scan Registers
them. Full boundary scan details can be found in the associated BSDL file which may be found on our web site
(www.IDT.com). The boundary scan chain is connected between TDI and TDO when the EXTEST or SAMPLE/PRELOAD
instructions are selected. Once EXTEST is selected and the TAP controller passes through the UPDATE-IR state, what-
ever value that is currently held in the boundary scan register’s output latches is immediately transferred to the corre-
sponding outputs or output enables.
so that inappropriate values are not driven out onto the system pins. All of the boundary scan cells feature a negative edge
latch, which guarantees that clock skew cannot cause incorrect data to be latched into a cell. The input cells are sample-
only cells.
The 80KSBR200 boundary scan chain is 140 bits long. The five JTAG pins do not have scan elements associated with
Therefore, the SAMPLE/PRELOAD instruction must first be used to load suitable values into the boundary scan cells,
The simplified logic configuration is shown in the figure below.
The simplified logic configuration of the output cells is shown in the figure below.
Input
Pin
Data from Previous Cell
shift_dr
clock_dr
From previous cell
Data from Core
shift_dr
Figure 43 Diagram of Observe-only Input Cell
137 of 172
clock_dr
Figure 44 Diagram of Output Cell
EXTEST
update_dr
D
D
Q
To Next Cell
Q
D
To Output Pad
To core logic
To next cell
Q
Advanced Datasheet*
March 19, 2007