80ksbr200 Integrated Device Technology, 80ksbr200 Datasheet - Page 160

• Manufacturer Part Number: 80ksbr200
• Description: Srio Serial Buffer Flow-control Device
• Manufacturer: Integrated Device Technology

„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a
Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
V21
AB3
AA3
V1
U1
L1
M1
L4
L3
J1
H1
J4
J3
P1
P2
P4
N4
F1
F2
F4
G4
RDO_N
REFCLKN
REFCLKP
REXTN
REXTP
S1_RXN0
S1_RXP0
S1_RXN1
S1_RXP1
S1_RXN2
S1_RXP2
S1_RXN3
S1_RXP3
S1_TXN0
S1_TXP0
S1_TXN1
S1_TXP1
S1_TXN2
S1_TXP2
S1_TXN3
S1_TXP3
Read Strobe
SERDES Clock
SERDES Clock
Rext
Rext
Port 1 Receive
Port 1 Receive
Port 1 Receive
Port 1 Receive
Port 1 Receive
Port 1 Receive
Port 1 Receive
Port 1 Receive
Port1 Transmit
Port1 Transmit
Port1 Transmit
Port1 Transmit
Port1 Transmit
Port1 Transmit
Port1 Transmit
Port1 Transmit
(VDD, GND) / CMOS Output
(VDD, GND) / Differential Input
(VDD, GND) / Differential Input
(VDDS, GNDS) /
S-Port 1 Differential Input
(VDDS, GNDS) /
S-Port 1 Differential Input
(VDDS, GNDS) /
S-Port 1 Differential Input
(VDDS, GNDS) /
S-Port 1 Differential Input
(VDDS, GNDS) /
S-Port 1 Differential Input
(VDDS, GNDS) /
S-Port 1 Differential Input
(VDDS, GNDS) /
S-Port 1 Differential Input
(VDDS, GNDS) /
S-Port 1 Differential Input
(VDDS, GNDS) /
S-Port 1 Differential Output
(VDDS, GNDS) /
S-Port 1 Differential Output
(VDDS, GNDS) /
S-Port 1 Differential Output
(VDDS, GNDS) /
S-Port 1 Differential Output
(VDDS, GNDS) /
S-Port 1 Differential Output
(VDDS, GNDS) /
S-Port 1 Differential Output
(VDDS, GNDS) /
S-Port 1 Differential Output
(VDDS, GNDS) /
RIO Differential Output
160 of 172
When QDR type SRAM attached, this output should be con-
nected to the /Rd input on the QDR SRAM(s). The FIFO control-
ler will use this pin to control the read function on the SRAM.
Negative side of differential input clock. This clock is used as the
156MHz reference for standard SERDES operation.
Positive side of differential input clock. This clock is used as the
156MHz reference for standard SERDES operation.
External bias resistor. This pin must be connected to Rextp with a
12k Ohm resistor. This establishes the drive bias on the SERDES
output. This provides CML driver stability across process and
temperature.
External bias resistor. This pin must be connected to Rextn with a
12k Ohm resistor.
Negative end of differential receiver, S-Port, Lane 0
Positive end of differential receiver, S-Port, Lane 0
Negative end of differential receiver, S-Port, Lane 1
Positive end of differential receiver, S-Port, Lane 1
Negative end of differential receiver, S-Port, Lane 2
Positive end of differential receiver, S-Port, Lane 2
Negative end of differential receiver, S-Port, Lane 3
Positive end of differential receiver, S-Port, Lane 3
Negative end of differential transmitter, S-Port, Lane 0
Positive end of differential transmitter, S-Port, Lane 0
Negative end of differential transmitter, S-Port, Lane 1
Positive end of differential transmitter, S-Port, Lane 1
Negative end of differential transmitter, S-Port, Lane 2
Positive end of differential transmitter, S-Port, Lane 2
Negative end of differential transmitter, S-Port, Lane 3
Positive end of differential transmitter, S-Port, Lane 3
Advanced Datasheet*
March 19, 2007