80ksbr200 Integrated Device Technology, 80ksbr200 Datasheet - Page 142

• Manufacturer Part Number: 80ksbr200
• Description: Srio Serial Buffer Flow-control Device
• Manufacturer: Integrated Device Technology

„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a
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IDT 80KSBR200
Notes
15.7 JTAG Configuration Register Access
The same JTAG instruction (4b1010) is used for both writes and reads.
15.7.1 Writes during Configuration Register Access
select bit, then both the 22-bit target address and 32-bit data into the Data Register (DR). When bit 0 of the data stream is
0, data shifted in after the address will be written to the address specified in jtag_config_addr. The TDO pin will transmit all
0s. See the figure below for the associated timing diagram.
15.7.2 Reads during Configuration Register Access
will be read from the address specified in jtag_config_addr. TDI will not be used after the address is shifted in. As a func-
tion of read latency in the architecture, the first 16 bits will be 0’s and must be ignored. The following bits will contain the
actual register bits.
As previously mentioned, the JTAG port may be used to read and write to the 80KSBR200’s configuration registers.
A write is performed by shifting the CRA OPcode into the Instruction Register (IR), then shifting in first a read / write
Reads are much like writes except that target data is not provided. When bit 0 of the data stream is 1, data shifted out
0
[22:1]
[54:23]
Bits
jtag_config_wr_n
jtag_config_addr
jtag_config_data
Field Name
Figure 47 Implementation of write during configuration register access
Table 107 Data Stream for JTAG Configuration Register Access Mode
142 of 172
1
22
32
Size
1 – read configuration register
0 – write configuration register
Starting address of the memory mapped configuration register. 22
address bits map to a unique double-word aligned on a 32-bit bound-
ary. This provides accessibility to and is consistent with the sRIO
memory mapping.
Reads: Data shifted out (one 32-bit word per read) is read from the
configuration register at address jtag_config_addr.
Writes: Data shifted in (one 32-bit word per write) is written to the con-
figuration register at address jtag_config_addr.
Description
Advanced Datasheet*
March 19, 2007