80ksbr200 Integrated Device Technology, 80ksbr200 Datasheet - Page 131

• Manufacturer Part Number: 80ksbr200
• Description: Srio Serial Buffer Flow-control Device
• Manufacturer: Integrated Device Technology

„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a
Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Notes
14.0 Parallel Port Electrical Characteristics
the external SRAM. The P-Port may also be disabled.
Burst 4 compatible. Included in the Parallel Port Requirements is the need for programmable output impedance as is used
in the QDRII SRAM. This includes the attachment of an external resistor to set the impedance.
four lanes, the maximum data rate is 10G bps across the interface in each direction. The external memories are all burst of
four. The clock rate on the bus is specified at 156.25 MHz. The 156.25 MHz is sufficient to support the 10G bps total band-
width in each direction necessary on the P-Port.
14.1 AC Electrical Characteristics
devices at HSTL levels. While QDRII has the ability to operate at 1.8V and other voltages in between 1.8V and HSTL,
there is no requirement for the SerB to operate beyond HSTL. There will be a direct connection from the P-Port to the
memory. The drive requirements of the interface will be HSTL Class 1 or less. There is a ZQ pin for setting interface imped-
ance.
clocking include the following:
The parallel port on the SerB can connect to a QDRII-B4 x36 SRAM. The SerB acts as a memory controller and drives
The electrical requirements of the P-Port are simply must be QDRII compatible. As a FIFO controller, the SerB must be
The Serial interface operate at 3.125G bps with 8B/10B encoding on each lane. After decoding and alignment of the
Please refer to figure below for SerB to external QDRII SRAM interface connections.
In this mode, the P-Port electrical characteristics and interface shall be fully compliant with designated QDRII SRAM
When connected to a QDR memory, the specific needs of the QDRII device must be met. The P-Port to QDR SRAM
Please refer to table below for specific AC Electrical Characteristics requirements.
The P-Port output clock / QDR input clock shall be center aligned and designed to clock the QDRII SRAM K/
K# input clock.
The P-Port input clock shall be edge aligned and designed to connect to the CQ/CQ# output of the QDRII
SRAM. It is strongly suggested that the C/C# clocks not be returned to the SerB P-Port.
The SerBs PHY clock is used internally to generate the P-Port output clock
Serial Buffer
P-Port
Figure 39 P-Port Signals Connected to a QDRII SRAM
131 of 172
Address(23)
K, K# (center)
Wr#
Rd#
D(36)
Q(36)
CQ, CQ# (edge)
SA
K, K#
Wr#
Rd#
D(36)
Q(36)
CQ, CQ#
C/ C#
BW(4)
QDR2 SRAM
Advanced Datasheet*
March 19, 2007