80ksbr200 Integrated Device Technology, 80ksbr200 Datasheet - Page 112

• Manufacturer Part Number: 80ksbr200
• Description: Srio Serial Buffer Flow-control Device
• Manufacturer: Integrated Device Technology

„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a
Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Notes
after the default configuration is active, the user should be aware that data or additional configuration information might be
accepted on multiple ports. The user must exercise care to insure that the incoming configuration and data does not inter-
fere with the device programming. In many cases, a partial reset may clear unwanted data, but may cause corruption of
active transfers.
9.5 Initialization of RIO Ports
the following references should be made:
Before operation, the SerB must be configured. The steps of configuration are as follows:
The sRIO ports shall be initialized before they are operational. More needs to be developed on this topic, but as a start,
The initialization of the sRIO ports may be influenced by the following sources:
Power on. No power sequencing is required, but all power supplies must have achieved the minimum required
level before proceeding.
Master reset may be applied at any time. If reset is performed in association with Power on, reset may be
applied before, during or after Power On, but the reset must be held after achieving valid power levels for the
designated minimum number of clock cycles (defined in the electrical section).
SerB will initialize itself according to the hard-wired pins.
–
–
–
I
registers may be programmed through I
JTAG has access to the configuration registers. If JTAG is not used for additional programming, the JTAG
inputs should be disabled. Full operation of JTAG is described in the JTAG section.
In the event that the SerB needs to be programmed over a serial port, the serial port must have achieved full
Link Up status before programming may commence.
If interrupt masks are needed, the masks should be programmed using one of the programming methods.
After programming, the SerB should be fully functional. It should be noted that the SerB may be reconfigured
at any time. It should be noted that at any time, the SerB may reconfigured through I
PPS specification an sRIO port Initialization
RIO Physical Layer Specification section 4.6
RIO System Bring-up document for explanation and examples of system bring-up
Hard-wired pin description
sRIO maintenance packets
I
JTAG programming
Hard-wired inputs
2
2
C may be used for additional programming if required without waiting for PLL lock. All of the configuration
C programming
The PLLs will take time to lock
The PHYs will begin to negotiate with neighboring devices, attempting to establish links
The memory will be allocated, per the default configuration
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2
C.
Advanced Datasheet*
2
C or a Serial Port.
March 19, 2007