80ksbr200 Integrated Device Technology, 80ksbr200 Datasheet - Page 135

• Manufacturer Part Number: 80ksbr200
• Description: Srio Serial Buffer Flow-control Device
• Manufacturer: Integrated Device Technology

„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a
Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Notes
15.0 JTAG Interface
“pins-down” testing of newly manufactured printed circuit boards as well as troubleshooting of field returns. The JTAG TAP
interface also offers an alternative method for Configuration Register Access (CRA) (along with the sRIO and I
Thus this port may be used for programming the SerB’s many registers.
15.1 IEEE 1149.1 (JTAG) & IEEE 1149.6 (AC Extest) Compliance
1149.1 and 1149.6 boundary scan cells are on the same chain. No additional control cells are provided for independent
selection of negative and/or positive terminals of the TX- or RX-pairs.
15.2 System Logic TAP Controller Overview
perform a variety of functions. The primary use of the JTAG TAP Controller state machine is to allow the five external JTAG
control pins to control and access the SerB's many external signal pins. The JTAG TAP Controller can also be used for
identifying the device part number. The JTAG logic of the 80KSBR200 is depicted in the figure below.
15.3 Signal Definitions
the table below. A functional overview of the TAP Controller and Boundary Scan registers is provided in the sections
following the table.
The 80KSBR200 offers full JTAG (Boundary Scan) support for both its slow speed and high speed pins. This allows
Boundary scan testing of the AC-coupled IOs is performed in accordance with IEEE 1149.6 (AC Extest).
All DC pins are in full compliance with IEEE 1149.1 [10]. All AC-coupled pins fully comply with IEEE 1149.6 [11]. All
The system logic utilizes a 16-state, six-bit TAP controller, a four-bit instruction register, and five dedicated pins to
JTAG operations such as Reset, State-transition control and Clock sampling are handled through the signals listed in
TRST
TCK
TMS
Pin Name
TRST
TDI
TMS
TCK
Type
Input
Input
Input
JTAG RESET
JTAG Clock
Test logic clock. JTAG_TMS and JTAG_TDI are sampled on the rising edge. JTAG_TDO is output
on the falling edge.
JTAG Mode Select. Requires an external pull-up.
Controls the state transitions for the TAP controller state machine (internal pull-up)
4-Bit Instruction Register
Bypass Register
Asynchronous reset for JTAG TAP controller (internal pull-up)
Instruction Register Decoder
Device ID Register
Boundary Scan Register
Table 103 JTAG Pin Descriptions (Part 1 of 2)
135 of 172
Figure 41 Diagram of the JTAG Logic
Tap Controller
Description
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Advanced Datasheet*
TDO
March 19, 2007
2
C ports).