80ksbr200 Integrated Device Technology, 80ksbr200 Datasheet - Page 86

• Manufacturer Part Number: 80ksbr200
• Description: Srio Serial Buffer Flow-control Device
• Manufacturer: Integrated Device Technology

„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a
Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Notes
Port 0 Packet Capture 1 CSR
written while actual physical layer errors are being detected by the port. Also, there could be latency between asserting an
interrupt from Output-Degraded Encountered or Output-Failed Encountered to loading this register, such that the interrupt
is asserted a few cycles before the error is captured into this register.
Port 0 Packet Capture 2 CSR
written while actual physical layer errors are being detected by the port. Also, there could be latency between asserting an
interrupt from Output-Degraded Encountered or Output-Failed Encountered to loading this register, such that the interrupt
is asserted a few cycles before the error is captured into this register
Port 0 Packet Capture 3 CSR
written while actual physical layer errors are being detected by the port. Also, there could be latency between asserting an
interrupt from Output- Degraded Encountered or Output-Failed Encountered to loading this register, such that the interrupt
is asserted a few cycles before the error is captured into this register.
Note:
Note:
Note:
Name:
Name:
Name:
Error capture register 1 contains bytes 4 through 7 of the packet header. Undefined results will occur if this register is
Error capture register 2 contains bytes 8 through 11 of the packet header. Undefined results will occur if this register is
Error capture register 3 contains bytes 12 through 15 of the packet header. Undefined results will occur if this register is
31:0
31:0
31:0
Bit
Bit
Bit
1.
1.
1.
P0_PKT_CAP_1_CSR
P0_PKT_CAP_2_CSR
P0_PKT_CAP_3_CSR
The above register is described in the RIO Specification Part 8, sec. 2.3.2.14
The above register is described in the RIO Specification Part 8, sec. 2.3.2.15
The above register is described in the RIO Specification Part 8, sec. 2.3.2.16
CAPT_1
CAPT_2
CAPT_3
Field Name
Field Name
Field Name
Table 46 Port 0 Packet/Control Symbol Capture 1 CSR
Table 47 Port 0 Packet/Control Symbol Capture 2 CSR
Table 48 Port 0 Packet/Control Symbol Capture 3 CSR
All 0s
All 0s
All 0s
Reset
Value
Reset
Value
Reset
Value
86 of 172
Address:
Address:
Address:
Capture 1: Control character and control symbol or Bytes 4 to 7 of
Packet Header.
Capture 2: Control character and control symbol or Bytes 8 to 11 of
Packet Header.
Capture 3: Control character and control symbol or Bytes 12 to 15 of
Packet Header.
0x000650
0x000654
0x000658
Comment
Comment
Comment
Advanced Datasheet*
March 19, 2007