80ksbr200 Integrated Device Technology, 80ksbr200 Datasheet - Page 165

• Manufacturer Part Number: 80ksbr200
• Description: Srio Serial Buffer Flow-control Device
• Manufacturer: Integrated Device Technology

„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a
Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
U6
U8
U10
U12
U14
A2
B1
C2
F3
G2
H3
M3
N2
P3
Y6
Y8
Y12
Y14
AA7
AA13
A21
VDD
VDD
VDD
VDD
VDD
VDD3
VDD3
VDD3
VDDA
VDDA
VDDA
VDDA
VDDA
VDDA
VDDA
VDDA
VDDA
VDDA
VDDA
VDDA
VDDQ
1.2V Digital
Power (CMOS)
1.2V Digital
Power (CMOS)
1.2V Digital
Power (CMOS)
1.2V Digital
Power (CMOS)
1.2V Digital
Power (CMOS)
2.5V / 3.3V
JTAG Power
(CMOS)
2.5V / 3.3V
JTAG Power
(CMOS)
2.5V / 3.3V
JTAG Power
(CMOS)
Analog Power
(CMOS)
Analog Power
(CMOS)
Analog Power
(CMOS)
Analog Power
(CMOS)
Analog Power
(CMOS)
Analog Power
(CMOS)
Analog Power
(CMOS)
Analog Power
(CMOS)
Analog Power
(CMOS)
Analog Power
(CMOS)
Analog Power
(CMOS)
Analog Power
(CMOS)
1.5V Digital
Power (CMOS)
165 of 172
Digital VDD. All pins must be tied to single potential power supply
plane.
Digital VDD. All pins must be tied to single potential power supply
plane.
Digital VDD. All pins must be tied to single potential power supply
plane.
Digital VDD. All pins must be tied to single potential power supply
plane.
Digital VDD. All pins must be tied to single potential power supply
plane.
Digital JTAG Pin VDD3. All pins must be tied to single potential
power supply plane.
Digital JTAG Pin VDD3. All pins must be tied to single potential
power supply plane.
Digital JTAG Pin VDD3. All pins must be tied to single potential
power supply plane.
Analog VDD. All pins must be tied to single potential power sup-
ply plane.
Analog VDD. All pins must be tied to single potential power sup-
ply plane.
Analog VDD. All pins must be tied to single potential power sup-
ply plane.
Analog VDD. All pins must be tied to single potential power sup-
ply plane.
Analog VDD. All pins must be tied to single potential power sup-
ply plane.
Analog VDD. All pins must be tied to single potential power sup-
ply plane.
Analog VDD. All pins must be tied to single potential power sup-
ply plane.
Analog VDD. All pins must be tied to single potential power sup-
ply plane.
Analog VDD. All pins must be tied to single potential power sup-
ply plane.
Analog VDD. All pins must be tied to single potential power sup-
ply plane.
Analog VDD. All pins must be tied to single potential power sup-
ply plane.
Analog VDD. All pins must be tied to single potential power sup-
ply plane.
Digital VDD. All pins must be tied to single potential power supply
plane.
Advanced Datasheet*
March 19, 2007