80ksbr200 Integrated Device Technology, 80ksbr200 Datasheet - Page 11

• Manufacturer Part Number: 80ksbr200
• Description: Srio Serial Buffer Flow-control Device
• Manufacturer: Integrated Device Technology

„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a
Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Notes
1.1.5
processor in the event of error conditions within the device. Refer to the Error Management section for full detail.
1.1.6 Reset
Reset & Initialization section for full detail.
1.1.7 Clock
detail.
1.1.8 R-Ext (Rextn & Rextp)
pins must be connected to one another with a 12k Ohm resistor. This provides CML driver stability across process and
temperature.
1.1.9 SPD[1:0]
quent programming of the Serial Port Configuration Register. SPD[1:0] = {00 = 1.25G, 01 = 2.5G, 10 = 3.125G, 11 =
RESERVED}. These pins must remain STATICALLY BIASED after power-up.
An interrupt output is provided in support of Error Management functionality. This output may be used to flag a host
A single Reset pin is used for full reset of the SerB, including setting all registers to power-up defaults. Refer to the
The single system clock (REF_CLK+ / -) is a 156.25 MHz differential clock input. Refer to the Clock section for full
These pins are used to establish the drive bias on the SERDES output. An external bias resistor is required. The two
Speed Select Pins. These pins define the sRIO port speed at RESET. The RESET setting may be overridden by subse-
Interrupt (IRQ)
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Advanced Datasheet*
March 19, 2007