80ksbr200 Integrated Device Technology, 80ksbr200 Datasheet - Page 7

• Manufacturer Part Number: 80ksbr200
• Description: Srio Serial Buffer Flow-control Device
• Manufacturer: Integrated Device Technology

„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a
Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Notes
List of Figures
Figure 1: Diagram of SerB Interfaces
Figure 2: PPS Data Storage
Figure 3: Generic sRIO Request Packet
Figure 4: sRIO Physical Layer Header
Figure 5: Transaction Types (8 or 16)
Figure 6: Transaction ID Range for sRIO Packet Generating Entities
Figure 7: sRIO Maintenance Request Packet (Type 8)
Figure 8: sRIO Maintenance Response Packet (Type 8)
Figure 9: Typical sRIO Packet showing location of Source and Destination IDs
Figure 10: sRIO Doorbell Packet
Figure 11: Reset Timeline
Figure 12: REF_CLK Representative Circuit
Figure 13: AC Output Test Load (JTAG)
Figure 14: AC Output Test Load (I2C)
Figure 15: sRIO Lanes Test Load
Figure 16: Write Protocol with 10-bit Slave Address (ADS = 1)
Figure 17: Read Protocol with 10-bit Slave Address (ADS = 1)
Figure 18: Write Protocol with 7-bit Slave Address (ADS = 0)
Figure 19: Read Protocol with 7-bit Slave Address (ADS = 0)
Figure 20: I2C SDA & SCL DC Electrical Specifications (VDD3 = 3.3V)
Figure 21: I2C SDA & SCL DC Electrical Specifications (VDD3 = 2.5V)
Figure 22: Specification of the SDA & SCL bus lines for F/S-mode I2C-bus Device
Figure 23: I2C Timing Waveform
Figure 24: Differential Peak-Peak Voltage of Transmitter or Receiver
Figure 25: Short Run Transmitter AC Timing Specifications - 1.25 GBaud
Figure 26: Short Run Transmitter AC Timing Specifications - 2.5 GBaud
Figure 27: Short Run Transmitter AC Timing Specifications - 3.125 GBaud
Figure 28: Long Run Transmitter AC Timing Specifications - 1.25 GBaud
Figure 29: Long Run Transmitter AC Timing Specifications - 2.5 GBaud
Figure 30: Long Run Transmitter AC Timing Specifications - 3.125 GBaud
Figure 31: Transmitter Output Compliance Mask
Figure 32: Transmitter Differential Output Eye Diagram Parameters
Figure 33: Receiver AC Timing Specifications - 1.25 GBaud
Figure 34: Receiver AC Timing Specifications - 2.5 GBaud
Figure 35: Receiver AC Timing Specifications - 3.125 GBaud
Figure 36: Single Frequency Sinusodial Jitter Limits
Figure 37: Receiver Input Compliance Mask
Figure 38: Receiver Input Compliance Mask Parameters Exclusive of Sinusodial Jitter
Figure 39: P-Port Signals Connected to a QDRII SRAM
Figure 40: Timing Waveform of Combined Read and Write Cycles
Figure 41: Diagram of the JTAG Logic
Figure 42: State Diagram of the 80KSBR200’s TAP Controller
Figure 43: Diagram of Observe-only Input Cell
Figure 44: Diagram of Output Cell
Figure 45: Diagram of Output Enable Cell
Figure 46: Diagram of Bi-directional Cell
Figure 47: Implementation of Write during Configuration Register Access
Figure 48: Implementation of Read during Configuration Register Access
Figure 49: JTAG DC Electrical Specifications (VDD3 = 3.3V)
Figure 50: JTAG DC Electrical Specifications (VDD3 = 2.5V)
Figure 51: JTAG AC Electrical Specifications
Figure 52: JTAG Timing Specifications
7 of 172
Advanced Datasheet*
March 19, 2007
13
18
19
19
22
23
23
27
33
111
113
115
116
116
118
118
119
119
119
120
120
121
123
124
125
125
125
126
126
127
127
128
128
129
129
130
130
131
133
135
136
137
137
138
138
142
143
143
143
144
144
10