80ksbr200 Integrated Device Technology, 80ksbr200 Datasheet - Page 132

• Manufacturer Part Number: 80ksbr200
• Description: Srio Serial Buffer Flow-control Device
• Manufacturer: Integrated Device Technology

„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a
Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Notes
Note:
1.
2.
3.
4.
5.
6.
input clock are stable.
(tKHKH).
time (tKHKH).
Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
Vdd slew rate must be less than 0.1V DC per 50ns for DLL lock retention. DLL lock time begins once Vdd and
If C, C are tied High, K, K become the references for C, C timing parameters.
All address inputs must meet the specified setup and hold times for all latching clock edges.
Clock to Clock time (tKHKH) and Clock to Clock time (tKHKH) should be within 45% to 55% of the duty cycle
Clock High time (tKHKL) and Clock Low time (tKLKH) should be within 40% to 60% of the duty cycle time
Clock Parameters
tKHKH
tKC var
tKHKL
tKLKH
tKHKH
tKHKH
tKHCH
tCK lock
tKC reset
Output Parameters
tCHQV
tCHQX
tCHCQV
tCHCQX
tCQHQV
tCQHQX
tCHQZ
tCHQX1
Set-Up Times
tAVKH
tIVKH
tDVKH
Hold Times
tKHAX
tKHIX
tKHDX
Symbol
Clock Cycle Time (K,K,C,C)
Clock Phase Jitter (K,K,C,C)
Clock High Time (K,K,C,C)
Clock Low Time (K,K,C,C)
Clock to clock (K K,C C)
Clock to clock (K K,C C)
Clock to data clock (K C,K C)
DLL lock tim (K, C)
K static to DLL reset
C, C HIGH to output valid
C, C HIGH to output hold
C, C HIGH to echo clock valid
C, C HIGH to echo clock hold
CQ, CQ HIGH to output valid
CQ, CQ HIGH to output hold
C HIGH to output High-Z
C HIGH to output Low-Z
Address valid to K, K rising edge
R, W inputs valid to K, K rising edge
Data-in valid to K, K rising edge
K, K rising edge to address hold
K, K rising edge to R, W inputs hold
K, K rising edge to data-in hold
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Table 102 AC Electrical Characteristics
Parameter
156.25MHz
1024
-0.50
-0.50
-0.40
-0.50
Min.
6.00
2.40
2.40
2.70
2.70
0.00
0.50
0.50
0.50
0.50
0.50
0.50
30
-
-
-
-
-
Max.
8.40
0.20
2.80
0.50
0.50
0.40
0.50
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
cycles
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Advanced Datasheet*
Notes
1
5
5
6
6
2
3
3
3
3
3
3
4
6
March 19, 2007