80ksbr200 Integrated Device Technology, 80ksbr200 Datasheet - Page 113

• Manufacturer Part Number: 80ksbr200
• Description: Srio Serial Buffer Flow-control Device
• Manufacturer: Integrated Device Technology

„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a
Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Notes
10.0 Reference Clock
the PHY Reference clock operating at 156.25M Hz. The following clocks are used within the SerB:
10.1 Reference Clock Electrical Specifications
comes from the sRIO specification that outgoing signals from separate links, which belong to the same port, should not be
separated more than 100ppm.
are associated with the input structure internal to the device. V
There are several clocks associated with the SerB. All internal operational clocks within the SerB are generated from
The reference clock is 156.25 MHz, and is AC-coupled with the following electrical specifications:
The reference clock wander should not be more than 100ppm (for 156.25 Mhz, this is +/-15.625 KHz). This requirement
Note that the series capacitors are descretes that must be placed external to the devices’s receivers. All other elements
REF_CLK_N
REF_CLK_P
Name
REF_CLK
tDUTY_REF
tRCLK/tFCLK
vIN_CML
RL_CLK
LI_CLK
CI_CLK
1.
2.
3.
functions. When P-Port is a QDR memory port, the PHY Reference clock also drives the memory interface.
PHY Reference Clock. This clock is an input at 156.25M Hz and is used to drive the serial ports and internal
JTAG Clock
I
2
C Clock
Description
REF_CLK clock running at 156.25Mhz
REF_CLK duty cycle
Input signal rise/fall time (20%-80%)
Differential peak-peak REF_CLK input swing
Input termination resistance
Input inductance
Input capacitance
Table 96 Input Reference Clock Jitter Specifications
C
C
L
113 of 172
L
V
Figure 12 REF_CLK representative circuit
I
I
I
I
, CLK
, CLK
, CLK
, CLK
BIAS
, CLK
BIAS
is generated internally.
R
R
L
L
5686 drw07
,CLK
,CLK
Min
-100
40
200
400
40
-----
-----
+
-
Nom
50
500
50
----
----
-----
-----
Advanced Datasheet*
Max
+100
60
650
2400
60
4
5
March 19, 2007
Units
ppm
%
ps
mV
ohm
nH
pF
REF_CLK