80ksbr200 Integrated Device Technology, 80ksbr200 Datasheet - Page 111

• Manufacturer Part Number: 80ksbr200
• Description: Srio Serial Buffer Flow-control Device
• Manufacturer: Integrated Device Technology

„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a
Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Notes
9.0 Reset and Initialization
4096 REF_CLK cycles later, the device completes the reset process. Once completed, access to the SerB from any and all
interfaces is possible and the SerB is fully functional. COntrol and data traffic will not be accepted by the SerB until this
process is fully completed.
9.1 Speed Select (SPD[1:0])
given below:
9.2 sRIO Reset Control Symbol
level reset and must be received four times to perform the reset. Despite it being a control symbol generated at the link
level, the use of the reset is generally instructed from higher-level authority than the link.
master reset, or as an sRIO port reset only. The PPS also has the capability of receiving instructions from the DSP to send
a control symbol on any one of its ports to reset other attached devices.
control symbol has been received four times. The count of four will reset whenever a packet other than an sRIO reset
control symbol is successfully received. The control symbol has no capability to form anything other than a Master Reset.
Any other sRIO resets must be received in the form of type 8 maintenance packets.
9.3 JTAG Reset
specification, the user can alternatively hold TMS pin high while clocking TCK five times (minimum) to reset the controller.
other JTAG input pins are internally biased in such a way that by leaving them unconnected they are automatically
disabled. Note that JTAG inputs are OK to float because they have leakers (as required by IEEE 1149.1 specification).
9.4 System Initialization
the duration of the default configuration, the SerB will not accept packets on either serial port. Once the SerB has achieved
the default configuration, the ports will become active and may accept data. If additional programming is to be completed
The SerB does not require specific power sequencing between any of the core and I/O supplies.
To reset the device, first reset signal has to be de-asserted (Reset Low), and it is asserted after 5 REF_CLK cycles.
There are 2 port speed select pins. These pins are used to chose the initial speed on sRIO ports. The selection table is
The sRIO Reset Control Symbol is defined by the RIO spec to perform a master reset on the target device. It is a link
The PPS has taken the control symbol and has allowed the user to program the severity of the reset either as a full
The SerB will not have the capabilities of the PPS and will perform only a full Master Reset whenever the sRIO reset
More details on the control symbol can be found in section 3.4.5.1 of Physical Layer x1/x4 LP-Serial Specification.
At Power-Up, TRST must be asserted LOW to bring the TAP controller up in a known, reset state. Per IEEE 1149.1
To deactivate JTAG, TRST should be tied low so that the TAP controller remains in a known state at all times. All of the
The SerB will automatically configure itself upon power up to the default configuration set by the hard-wired inputs. For
Value on the Pins (SPD1 SPD0)
111 of 172
Table 95 Port Speed Selection Pin Values
00
01
10
11
Figure 11 Reset Timeline
o r t s R a t e
3.125Gbps
1.25Gbps
Reserved
2.5Gbps
Advanced Datasheet*
March 19, 2007