80ksbr200 Integrated Device Technology, 80ksbr200 Datasheet - Page 147

• Manufacturer Part Number: 80ksbr200
• Description: Srio Serial Buffer Flow-control Device
• Manufacturer: Integrated Device Technology

„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a
Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
AA19
Y22
V21
W22
V18
V22
U18
C6
U3
V3
E21
E22
H18
G18
A14
A15
A16
A17
A18
A19
A20
ADS
AUXCKI
AUXCKQ
CKI
CKI_N
CKO
CKO_N
QDR ADDR 14
QDR ADDR 15
QDR ADDR 16
QDR ADDR 17
QDR ADDR 18
QDR ADDR 19
QDR ADDR 20
I
AUX ClockI
AUX ClockQ
P-Port Clock
P-Port Clock
Echo Clock
Echo Clock
2
C
(VDDQ, GND) / CMOS Output
(VDDQ, GND) / CMOS Output
(VDDQ, GND) / CMOS Output
(VDDQ, GND) / CMOS Output
(VDDQ, GND) / CMOS Output
(VDDQ, GND) / CMOS Output
(VDDQ, GND) / CMOS Output
(VDD, GND) / CMOS Input
(VDD, GND) / CMOS Input
(VDD, GND) / CMOS Input
(VDD, GND) / CMOS Output
(VDD, GND) / CMOS Output
147 of 172
When operating as a FIFO controller, the A output is the address
for the external memory and should be connected directly to the
SA lines on the QDRII B4 SRAM.
When operating as a FIFO controller, the A output is the address
for the external memory and should be connected directly to the
SA lines on the QDRII B4 SRAM.
When operating as a FIFO controller, the A output is the address
for the external memory and should be connected directly to the
SA lines on the QDRII B4 SRAM.
When operating as a FIFO controller, the A output is the address
for the external memory and should be connected directly to the
SA lines on the QDRII B4 SRAM.
When operating as a FIFO controller, the A output is the address
for the external memory and should be connected directly to the
SA lines on the QDRII B4 SRAM.
When operating as a FIFO controller, the A output is the address
for the external memory and should be connected directly to the
SA lines on the QDRII B4 SRAM.
When operating as a FIFO controller, the A output is the address
for the external memory and should be connected directly to the
SA lines on the QDRII B4 SRAM.
I
address. ADS = Vdd for 10-bit. NOTE: SUPPLY / LEVELS
REQUIREMENTS ARE UNQUE FROM THE OTHER I
Auxiliary clocks provided to bypass CDR block for DC-type test-
ing of SERDES RX inputs.
Auxiliary clocks provided to bypass CDR block for DC-type test-
ing of SERDES RX inputs.
Clock input for the P-Port. These inputs should be connected to
the CQ/nCQ outputs of the QDR SRAM when operating as a
FIFO controller.
Clock input for the P-Port. These inputs should be connected to
the CQ/nCQ outputs of the QDR SRAM when operating as a
FIFO controller.
Clock output that is closely aligned with parallel port data output
(Q), address (A), Queue Empty (E), and Queue Full (F). When
operating as a FIFO controller, outputs read (nRd), and write
(nWr) are also aligned. The alignment is selectable as either cen-
ter aligned or edge aligned in the configuration register. When
PPM is LOW, this output should be connected to the K and nK
inputs of the QDR SRAM.
Clock output that is closely aligned with parallel port data output
(Q), address (A), Queue Empty (E), and Queue Full (F). When
operating as a FIFO controller, outputs read (nRd), and write
(nWr) are also aligned. The alignment is selectable as either cen-
ter aligned or edge aligned in the configuration register. When
PPM is LOW, this output should be connected to the K and nK
inputs of the QDR SRAM.
2
C address width select. Set ADS = GND for 7-bit SerB slave
Advanced Datasheet*
March 19, 2007
2
C PINS.