80ksbr200 Integrated Device Technology, 80ksbr200 Datasheet - Page 136

• Manufacturer Part Number: 80ksbr200
• Description: Srio Serial Buffer Flow-control Device
• Manufacturer: Integrated Device Technology

„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a
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IDT 80KSBR200
Notes
the rising edge of TCK. The Test-Logic Reset state can be reached either by asserting TRST or by applying a 1 to TMS for
five consecutive cycles of TCK. A state diagram for the TAP controller appears in
sent the value that must be applied to TMS on the next rising edge of TCK, to transition in the direction of the associated
arrow.
15.4 Test Data Register (DR)
described in the following sections. For more detailed descriptions, refer to IEEE Standard Test Access port (IEEE Std.
1149.1-1990).
The system logic TAP controller transitions from state to state, according to the value present on JTMS, as sampled on
The Test Data register contains the following:
These registers are connected in parallel between a common serial input and a common serial data output, and are
TDI
TDO
Pin Name
The Bypass register
The Boundary Scan registers
The Device ID register
Type
Output
Input
1
0
Figure 42 State Diagram of the 80KSBR200’s TAP Controller
Test- Logic
Run-Test/
Idle
JTAG Input
Serial data input for BSC chain, Instruction Register, IDCODE register, and BYPASS register
(internal pull-up)
JTAG Output
Serial data out. Tri-stated except when shifting while in Shift-DR and SHIFT-IR TAP controller
states.
Reset
Table 103 JTAG Pin Descriptions (Part 2 of 2)
0
136 of 172
0
1
1
0
1
Capture-DR
Exit2-DR
Shift-DR
Select-
DR-Scan
Exit1 -DR
Pause-DR
Update-DR
1
0
1
1
0
0
0
Description
0
1
0
1
0
1
1
Capture-IR
Shift-IR
Exit2-IR
Select-
IR-Scan
Exit1-IR
Pause-IR
Update-IR
Figure
1
0
1
0
0
1
1
0
41. The value next to state repre-
0
1
0
Advanced Datasheet*
March 19, 2007