80ksbr200 Integrated Device Technology, 80ksbr200 Datasheet - Page 146

• Manufacturer Part Number: 80ksbr200
• Description: Srio Serial Buffer Flow-control Device
• Manufacturer: Integrated Device Technology

„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a
Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
16.2 Pin Listing
IDT 80KSBR200
V17
AB19
W17
AB20
AA18
AA20
Y18
AA21
W18
Y20
W19
Y21
V19
AA22
Number
Pin
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
Pin Name
QDR ADDR 0
QDR ADDR 1
QDR ADDR 2
QDR ADDR 3
QDR ADDR 4
QDR ADDR 5
QDR ADDR 6
QDR ADDR 7
QDR ADDR 8
QDR ADDR 9
QDR ADDR 10
QDR ADDR 11
QDR ADDR 12
QDR ADDR 13
Function
(VDDQ, GND) / CMOS Output
(VDDQ, GND) / CMOS Output
(VDDQ, GND) / CMOS Output
(VDDQ, GND) / CMOS Output
(VDDQ, GND) / CMOS Output
(VDDQ, GND) / CMOS Output
(VDDQ, GND) / CMOS Output
(VDDQ, GND) / CMOS Output
(VDDQ, GND) / CMOS Output
(VDDQ, GND) / CMOS Output
(VDDQ, GND) / CMOS Output
(VDDQ, GND) / CMOS Output
(VDDQ, GND) / CMOS Output
(VDDQ, GND) / CMOS Output
Supply / Interface
Table 108 Pin Listing (Alphabetical)
146 of 172
When operating as a FIFO controller, the A output is the address
for the external memory and should be connected directly to the
SA lines on the QDRII B4 SRAM.
When operating as a FIFO controller, the A output is the address
for the external memory and should be connected directly to the
SA lines on the QDRII B4 SRAM.
When operating as a FIFO controller, the A output is the address
for the external memory and should be connected directly to the
SA lines on the QDRII B4 SRAM.
When operating as a FIFO controller, the A output is the address
for the external memory and should be connected directly to the
SA lines on the QDRII B4 SRAM.
When operating as a FIFO controller, the A output is the address
for the external memory and should be connected directly to the
SA lines on the QDRII B4 SRAM.
When operating as a FIFO controller, the A output is the address
for the external memory and should be connected directly to the
SA lines on the QDRII B4 SRAM.
When operating as a FIFO controller, the A output is the address
for the external memory and should be connected directly to the
SA lines on the QDRII B4 SRAM.
When operating as a FIFO controller, the A output is the address
for the external memory and should be connected directly to the
SA lines on the QDRII B4 SRAM.
When operating as a FIFO controller, the A output is the address
for the external memory and should be connected directly to the
SA lines on the QDRII B4 SRAM.
When operating as a FIFO controller, the A output is the address
for the external memory and should be connected directly to the
SA lines on the QDRII B4 SRAM.
When operating as a FIFO controller, the A output is the address
for the external memory and should be connected directly to the
SA lines on the QDRII B4 SRAM.
When operating as a FIFO controller, the A output is the address
for the external memory and should be connected directly to the
SA lines on the QDRII B4 SRAM.
When operating as a FIFO controller, the A output is the address
for the external memory and should be connected directly to the
SA lines on the QDRII B4 SRAM.
When operating as a FIFO controller, the A output is the address
for the external memory and should be connected directly to the
SA lines on the QDRII B4 SRAM.
Pin Function Description
Advanced Datasheet*
March 19, 2007