80ksbr200 Integrated Device Technology, 80ksbr200 Datasheet - Page 117

• Manufacturer Part Number: 80ksbr200
• Description: Srio Serial Buffer Flow-control Device
• Manufacturer: Integrated Device Technology

„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a
Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Notes
12.0 I
fications associated with the I
other details.
ization and management purposes. A CPU can then access registers and program the device, but it cannot access other
devices attached to the sRIO interfaces through the I
100 kHz). The SerB does NOT support CBUS or General Address calls.
12.1 I
10 external pins. This provides full flexibility in defining the slave address to avoid conflicting with other I
given bus. The SerB may be operated as either a 10-bit addressable device or a 7-bit addressable device based on
another external pin Address Select (ADS). If the ADS pin is tied to Vdd, then the SerB operates as a 10-bit addressable
device and the device address will be defined as ID[9:0]. If the ADS pin is tied to GND, then the SerB operates as a 7-bit
addressable device with the device address defined by ID[6:0]. The addressing mode must be established at power-up
and remain static throughout operation. Dynamic changes will result in undetermined behavior.
word boundaries though standard reads and writes. These registers may also be accessed through the sRIO and JTAG
interfaces.
12.2 Signaling
two cases:
The SerB is compliant with the I
The I
Relative to I
All of the SerB’s registers are addressable through I
The SerB is a slave-only receive and transmit device. Thus, communication with the SerB on the I
All signaling is fully compliant with I
1.
2.
2
C bus is comprised of Serial Data (SDA) and Serial Clock (SCL) pins and can be used to attach a CPU for initial-
2
2
C Device Address
–
–
–
–
–
–
Suppose a master device wants to send information to the SerB:
If a master device wants to receive information from the SerB:
C-Bus
2
C, the SerB is a slave-only receiver and transmitter. The device address for the SerB is fully pin-defined by
Master device addresses SerB (slave)
Master device (master-transmitter), sends data to SerB (slave- receiver)
Master device terminates the transfer
Master device addresses SerB (slave)
Master device (master-receiver) receives data from SerB (slave- transmitter)
Master device terminates the transfer.
2
C bus. This includes signaling, addressing, arbitration, AC timing, DC specifications, and
Table 101 I
2
C specification [1]. This specification provides all functional detail and electrical speci-
Pin
ID0
ID1
ID2
ID3
ID4
ID5
ID6
ID7
ID8
ID9
2
C. Full detail of signaling can be found in the I
117 of 172
2
C static address selection pin configuration
2
C bus. The I
2
I
0
1
2
3
4
5
6
7 (don’t care in 7-bit mode)
8 (don’t care in 7-bit mode)
9 (don’t care in 7-bit mode)
C. These registers are accessed via 22-bit addresses and 32-bit
2
C Address Bit (pin_addr)
2
C interface supports Fast/Standard (F/S) mode (400/
2
C specification [1].
Advanced Datasheet*
2
C bus follows these
March 19, 2007
2
C devices on a